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SVP is key technology for nanometer IC design

Posted: 16 Sep 2003 ?? ?Print Version ?Bookmark and Share

Keywords:silicon virtual prototyper? svp eda? soc? nanometer? deep-submicron process?

As we cross the 0.1?m process threshold, the challenges posed by shrinking processes represent moving targets for the EDA industry. Timing closure continues to be a critical issue because problems change with every development in process technology. Once the domain of the system-level designer, architectural issues must now be addressed at the chip level.

In the past, up until the 0.25?m process node, chips were simply components of larger systems and subsystems. Chip designers were not required to worry about architectural issues. With the advent of deep-submicron and nanometer processes, it is now possible to integrate an entire system onto a single chip. This means that the designer must now consider architectural issues. According to a study conducted by International Business Strategies, architecture represented a meager 2 percent of the overall design activity required to complete a chip at 0.35?m, but the architecture will rise to 26 percent of design activity at 90nm.

Physical hierarchy

At 90nm, it is possible to squeeze 100 million gates onto a single chip. Physical hierarchy is needed to deal with a chip of this size and complexity. Using a hierarchical design flow, the design team takes the chip-level constraints for timing, area and power, and maps them to block-level constraints, which are used to drive block implementation. Timing can then be closed on each of the physical blocks using conventional tools and flows.

However, timing closure at the top level cannot be achieved by conventional means. The reason for this is that there are inevitably variances between the block-level constraints and the actual characteristics of the fully implemented block. The variance is never known until the block is complete. Multiple-block variances may result in irresolvable conflicts at the chip level. New tools and methodologies are needed to close chip-level timing on hierarchical SoC designs.

Progressive refinement is a design methodology that enables chip design teams to get an accurate feedback on timing, power and area characteristics of the final physical implementation far in advance of the completion of the chip. There are a number of key elements to this approach. First, physical design must start at the same time as architectural and logic design. This is a dramatic difference from conventional design flows where the chip progresses sequentially from architecture to logic design, and finally to physical design.

Second, architectural and logic designers must accept the feedback that they receive from the physical design team and use that information to optimize the design for physical implementation. One of the key benefits of progressive refinement is that physical information is available almost immediately, so that catastrophic problems can be fixed by making adjustments to the architecture or logic design--problems that might be impossible to fix during physical implementation.

Third, progressive refinement is incremental. The process starts early with an initial chip-level design plan. At this point, the estimates available for block size, timing and power consumption may not be accurate, but the initial plan acts as a baseline against which to measure progress toward the completed chip. As more accurate information about the blocks becomes available, the chip-level plan is incrementally updated and any necessary adjustments are made.

Because this approach is radically different than conventional design flows, new technology and tools are required to provide the described benefits. The most important of these tools is the SVP.

An SVP is an accurate representation of the finished chip that provides information on timing, power and die size, and is constructed far in advance of the completion of the design. To be useful, the SVP must be available before the architecture and logic designs are finalized. Two key pieces of technology are required for an SVP tool: hierarchical design planning and silicon performance estimation.

The initial design plan must be constructed early in the process--during architectural and logic design. To support this, the hierarchical design planner must provide automated capabilities for block placement and shaping, top-down constraint budgeting, port placement and optimization, power network construction, global routing and hierarchy management.

Accurate silicon performance estimation requires additional capabilities including STA, physical synthesis, cell placement, power network construction and analysis, clock tree synthesis, parasitic extraction and global routing.

Chip-level design closure

As mentioned, one of the biggest challenges of hierarchical SoC design is closure at the chip level after all of the blocks have been completed. An SVP tool can greatly facilitate chip-level closure in the following manner.

Tight integration between the hierarchical design planner and the silicon performance estimator allows for instantaneous communication of all changes to the design at any level. The design planner passes block-level constraints to the estimator, which then uses them to drive the construction of block-level prototypes.

As soon as a prototype is available for a block, the design planner updates the chip-level plan with the new timing, power and area characteristics of the block. The design planner then incrementally analyzes the effects of the new information at the top level and on any of the other blocks. The design planner automatically adjusts the placement of the blocks and global routing, and then re-allocates power and timing slack. Problems that result from the new block information are identified immediately and the design team can then take the appropriate steps to resolve them.

A tightly integrated SVP tool also enables capabilities such as hierarchical IR drop analysis and timing optimization. Any change to the global power network is immediately communicated to all of the blocks so that the IR drop may be re-analyzed within each of the blocks. Timing paths that are composed of cells contained in different blocks spanning multiple hierarchical boundaries may be optimized without having to optimize each block individually. It is this combination of instantaneous communication, continuous monitoring and analysis, and incremental adjustment that enables the design team to progress predictably toward chip-level closure.

- Dave Reed

Marketing VP

Monterey Design Systems Inc.

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