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Interface deal links Artisan with Denali

Posted: 17 Sep 2003 ?? ?Print Version ?Bookmark and Share

Keywords:artisan components? denali software? memory? controller? dram?

Intellectual-property provider Artisan Components Inc. and memory controller specialist Denali Software Inc. have teamed to deliver near-turnkey IP for advanced double-data-rate (DDR) DRAM interfaces on system-level chips.

The companies said they hope to remove most of the issues that have made external memory interfaces a stumbling block to system-on-chip designs in recent months. Their deliverables will include system-level performance models, RTL code for Denali's DRAM controller core, a verification bench, scripts, closure guidelines, and compatibility charts.

"This relationship was drawn together by the needs of our mutual customers, but it was really catalyzed by the emergence of DDR as a memory interface on SoCs," said Mark Gogolewski, CTO at Denali Software. "With the advent of DDR, the interface to DRAM became so complex that it just will no longer work to gather up a bunch of point solutions and hook them together. You need a controller, delay lines, PLLs, I/O cells, timing data, and verification tools that already work together before you start."

Much of the problem is the rising data rate and signal frequency in DRAM interfaces. With conventional DRAMs - which provided most of the external memory for SoCs until this year - conventional I/O cells were sufficient. But SoC designers have been driving their need for speed to the edges of their dice and beyond. With 400MHz DDR interfaces starting to show up in SoC designs, conventional techniques and standard I/O cells no longer do the job.

A big part of the package in the new program from the two companies is compatibility matrices. This data indicates which I/O cells, PLL designs and analog delay lines need to be used together to meet the timing specs imposed by the controller.

Another big part of the package is direct involvement by Artisan support personnel. "We stay involved in the physical design with design reviews and on-site visits," said Nandan Nayampally, program manager at Artisan Components. In some cases the involvement will extend to helping a design team analyze the package and board environment that must be modeled along with the I/O cells to verify timing.

This problem will get worse in the future, said Artisan VP of engineering Behnam Malek-Khosravi. "The electrical problem has definitely expanded to include the package and the board. But it is becoming a modeling issue as well."

"Below 400MHz, the existing Ibis models work fine," said Malek. "But when you get to 800 Mbps - 400MHz on DDR interfaces - you have to start Spice-ing things. In some of the really fast interfaces we are seeing now, up around 2.5Gbps, even Spice isn't sufficient. You have to start doing 3D field analysis and paying careful attention to return paths."

While it will be a while before DRAM interfaces get into the gigahertz range, Denali is already supporting a PCI Express controller, which may be given the benefit of the working relationship between the library and controller vendors. And the program may eventually explore other high-speed interfaces as well, the companies said.

- Ron Wilson

EE Times

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