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Cadence, ARM release 'reference flow'

Posted: 19 Sep 2003 ?? ?Print Version ?Bookmark and Share

Keywords:cadence design systems? arm? reference methodology? buildgates synthesis? pks physical synthesis?

Cadence Design Systems and ARM have announced the ARM-Cadence Reference Methodology, described as a "shrink-wrapped reference flow" that includes ARM processor models and Cadence IC implementation tools.

The companies claim it will provide better timing, area and power estimates for ARM-based system-on-chip (SoC) designs.

The reference flow includes Cadence's SoC Encounter RTL-to-GDSII design system, which includes BuildGates synthesis, PKS physical synthesis, Nanoroute IC router and CeltIC crosstalk analyzer. Other tools supported in the flow include the Fire and Ice extractor, VoltageStorm power grid verifier and Verplex Conformal logic equivalence checker.

The ARM-Cadence Reference Methodology will be available from ARM in Q4, and will support the ARM946ES core initially. Support for all other ARM soft cores is expected in the future.

- Richard Goering

EE Times





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