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SoC backbone blends bursts, streams

Posted: 24 Sep 2003 ?? ?Print Version ?Bookmark and Share

Keywords:sonics? silicon backplane? interblock communications architecture? silicon backplane iii?

Intellectual property vendor Sonics Inc. has unveiled the third-generation (3G) version of Silicon Backplane, its interblock communications architecture. The collection of physical interconnect, traffic-shaping agents, open-specification block interfaces, modeling tools and development tools give designers a number of ways to link the functional blocks of a system-on-chip ICs.

In the Sonics architecture, user-defined functional modules such as CPUs, dedicated processors, memory blocks or peripheral controllers, are stripped of any protocol-dependent interconnect bus interface logic, leaving bare contact stubs. Standard hardware wrappers, known as Open Core Protocol (OCP) wrappers, connect these stubs to intelligent agents that send, receive and time shape flows for the block. These agents, in turn, communicate through a proprietary Sonics fabric.

Because the blocks are stripped of interface logic, they are independent of the physical implementation of the interconnect fabric. That promotes the reusability of blocks within design teams and across corporate boundaries, the company said. Broadening its marketing emphasis, Sonics is shifting away from OCP wrappers and toward the agents that control them.

James Colgan, director of product marketing at Sonic, said SoC designers are asking for a single DRAM pool rather than two or more external memory interfaces. They also need to deal with substantially higher data rates, a mix of video data and packet-oriented data, higher-resolution displays and digital recording.

Under these pressures, Colgan said that traditional microprocessor-bus-like interconnect architectures are breaking down. To meet this challenge, Sonics offers Silicon Backplane III as two different interconnect fabrics. Silicon Backplane III is used for bonding high-bandwidth blocks, and the Synapse 3220 fabric is used with standard OCP wrappers for collecting less demanding peripheral devices.

But the heavy lifting is done by the Silicon Backplane fabric. Much of the functionality of this smart fabric comes from the agents. An agent comprises two state machines, one for the OCP port and one for the fabric interface, with whatever buffer memory, flags and control registers the development software deems necessary for the agent to meet its requirements.

The agent's job is not simply to connect the OCP wrapper to the fabric, but to keep track of which data belongs to which execution threads within the chip, manage priorities for the data flows, shape and if necessary reorder the data. Thus embedded within the agents by the development software are many of the functions that sophisticated chip architects would normally develop ad-hoc inside the functional blocks of the design.

An important feature in Silicon Backplane III is the MemMax DRAM management block. Like other advanced DDR DRAM managers, MemMax can handle grouping and reordering of reads and writes to minimize DRAM latency. Because it is part of the Backplane, MemMax has information not available to normal DRAM controllers. The thread identifiers used for grouping and prioritizing data flows between agents, so the controller knows the source of a memory request and the data structure involved, not just the address range.

The architecture, coupled with its performance modeling and generation software, makes it feasible not only to reuse substantial blocks of IP unmodified, according to Sonics, but also removes much of the data flow architecting and tuning from a design team's schedule, generating a tuned interconnect solution from coarse architecture down to the programming of the agents. The impact on design time, particularly for an incremental design, can be enormous, the company said.

- Ron Wilson

EE Times

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