SynApps customizes its tools for users

Following an unusual business model, SynApps Software Corp. leverages in-house technology to offer customized EDA tools that perform static timing analysis, synthesis, placement, clock tree synthesis and simulation. The quiet company will further refine its tools to suit a customer's needs, said president and CEO Hirendu Vaishnav.

Founded by Vaishnav in 1997 as a consulting firm in a field outside electronic design, SynApps started to develop EDA software in 1999. Today, its customizable tool, Snap, offers capabilities for ASICs and structured ASICs. The five-person company counts Theseus Logic, NEC and MultiGig as customers.

"It's basically a new way of doing EDA," said Vaishnav. "We're an EDA company that will change its tools to how the users want it, when they want it, where they want it."

SynApps will address "any special needs customers might have that are not addressed by EDA vendors in a timely fashion," he said.

Before founding SynApps, Vaishnav was director of engineering at Sapphire Design Automation, a design-planning company subsequently purchased by Sequence Design Inc. Vaishnav also worked at Cadence Design Systems Inc. and Synopsys Inc., developing links between synthesis and layout tools for both companies.

Who needs customized EDA development? "Anyone who is pushing technology limits where they need algorithmic support. Anybody doing something different than pure mainstream, ASIC-based design," he said.

For example, SynApps worked with Theseus Logic to develop a static timing analysis capability for asynchronous logic--something not offered by commercial vendors, Vaishnav said. And the company developed a rotary clock insertion tool for MultiGig. A rotary clock can offer nearly zero skew, with power dissipation savings up to a couple of orders of magnitude, according to SynApps.

SynApps' internally developed Snap consists of modules such as parsers, elaborators, optimizers, readers/writers and engines for timing, delay, simulation, area and power. It includes what Vaishnav described as a complete static timing analysis and delay calculation capability. A timing engine for asynchronous blocks is available. The delay calculator supports a customized calculation based on physical data, in addition to data derived from libraries.

Snap supports VHDL and Verilog synthesis through its RTL compilation module, as well as its synthesis/technology mapping module. Users can buy the entire package, or use their own RTL compiler with the mapper. The elaborator comes from a third party.

Snap includes modules for standard and rotary clock tree insertion. The placement capability is purely cell-level, though hierarchical support is in development. Simulation is currently gate-level only. Vaishnav said SynApps is also developing IC routing.

An integrated database and a GUI pull the modules together. SynApps offers customized interface file formats.

Vaishnav said SynApps uses a "fully deployed" model: the company will go to a customer's site, learn its requirements, develop algorithms and customize EDA software. SynApps will then install the new tools and make sure they're working with the customer's design flow. A project is not complete, he said, until the SynApps software is fully integrated and deployed in a production EDA environment.

- Richard Goering

EE Times