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High-k, strained Si leaving the lab

Posted: 02 Oct 2003 ?? ?Print Version ?Bookmark and Share

Keywords:international electron devices meeting? transistor? cmos? plastic thin-film transistor? nanowire?

With performance improvements getting harder to wring out of CMOS by transistor shrinks, researchers are increasingly turning to strained silicon, high-k oxides and even different types of on-chip silicon-crystal orientation. At this year's International Electron Devices Meeting, a host of papers on these and other topics will show just how seriously the industry is pursuing techniques that were mere lab curiosities not long ago.

Scheduled for Dec. 8-10 in Washington, U.S.A., IEEE's 2003 IEDM is likely to be remembered for its eclectic nature. Plastic thin-film transistors, nanowires, and many other over-the-horizon technologies will be addressed in the 200 papers.

Intel Corp. will discuss a proposed solution to perhaps the most important challenge facing the semiconductor industry: how a high-k gate dielectric can be introduced without reducing the mobility of carriers moving through the channel. The industry's high-k development effort has moved into high gear, as leakage currents at the thin gate-insulation layer make it unlikely that silicon dioxide can be scaled much further.

Much high-k research is focused on hafnium oxide, but due to phonon scattering, that material can cut electron and hole mobility by 40 to 50 percent when used with polysilicon gate electrodes. The Intel team, based at the company's logic technology development center in Hillsboro, Oregon, deposited hafnium oxide directly above the strained-silicon channel without a buffer layer, cutting leakage current by a factor of 1,000, or three orders of magnitude.

Replacing the polysilicon electrode with a titanium nitride metal gate, Intel found that the metal gate helped reduce the coupling of the hafnium oxide phonons with the channel electrons during inversion. Moreover, the strain in the channel region also helped to reduce the mobility degradation normally observed with high-k oxides, according to the Intel team.

IBM Corp. will head into IEDM with 18 papers, among them a daring effort to combine two types of silicon with different crystalline structures on the same chip. The technique takes advantage of the fact that NFETs run faster in 100-orientation silicon, now the industry standard for silicon wafers, while PFETs are faster in a 110-orientation lattice.

The IBM team created a blocking mask to define all of the places on the die where PFETs are needed, and used epitaxial deposition techniques to deposit silicon with a 110 crystal orientation only where the PFET transistors are built. The result was a 65 percent improvement in PFET performance for 90nm devices, IBM reports-remarkable when the difficulty of speeding up the PFETs is considered.

The approach is not simple: It also requires bonding together two wafers with the 100 and 110 silicon, using layer transfer techniques. IBM calls the approach hybrid orientation technology, or HOT.

Jeff Welser, director of silicon-on-insulator (SOI) technology at IBM's Microelectronics Division, said the company has developed very precise epitaxial-deposition techniques for raised source and drain structures, which are likely to be implemented at the 65nm production node. Similar wafer-level epitaxial deposition techniques are able to contain the deposited area of 110-orientation silicon to the PFET regions. For the 45nm node, when HOT could be introduced, the 110 crystal deposition would need to be contained to a 0.1-by-0.1?m layout. "The selective epi for the raised source-drain structures is actually smaller than what we need for the PFETs made on 110 silicon," Welser said.

At IEDM, IBM also will present work on advanced strained-silicon techniques that do away with the relaxed silicon germanium layer. Conventional strained silicon uses a relatively thick layer of SiGe to exert a strain on a top layer of relatively thin silicon. The larger germanium atoms stretch or strain the top lattice of silicon, resulting in marked improvement of the NFETs, but much less of a performance boost for the PFETs.

At the 45nm node, Welser said, the need to thin the active-silicon and SiGe layers makes building the transistors on top of a SiGe layer too difficult for fully depleted SOI.

At the 45nm node, IBM is likely to move to a layer transfer approach, in which the strained-silicon layer is created atop a SiGe structure and then sliced away and deposited on top of an SOI wafer. That eliminates the SiGe layer; remarkably, the strain on the upper silicon layer is maintained without it, and during the thermal cycles of chip processing.

IBM calls this method SSDOI, for strained silicon directly on insulator.

The two approaches could be additive, with the SSDOI and HOT technologies combined. T.C. Chen, a VP at IBM Research, said the two techniques are relatively simple to implement using standard wafer-processing technologies. "Implementing either could provide the industry with higher-performing and lower-power chips; combining the techniques could generate even higher performance and lower power," Chen said.

The IBM SSDOI paper is among more than 16 papers on strained silicon that will be delivered at this year's IEDM, including two papers from Taiwan Semiconductor Mfg Co.

Intel shocked many in the industry last year by announcing that it would use some form of strained silicon at the 90nm process node. Engineering samples of the Prescott Pentium 4, built using the 90nm strained-silicon process, are now shipping.

There are many ways to induce strain, said Judy Hoyt, a professor at the Massachusetts Institute of Technology, who pioneered strained-silicon research while at Stanford University. NFETs respond better to tensile strain, while PFETs speed up under compressive strain. Strain can come from engineering the spacer layer, from the silicide or from the way the source and drain regions are built.

"It is hard to say at this point which technique will deliver the best devices. It's still up in the air about what's the right way to induce strain," Hoyt said.

Moving beyond silicon, several presentations at IEDM will focus on germanium MOSFETs, taking advantage of the higher transport speeds within germanium. An MIT graduate student, Andy Ritenour, working with MIT professor Gene Fitzgerald, will describe an early effort to apply strain techniques to germanium MOSFETs. A Stanford University research group will tackle the difficult issue of integrating germanium NFETs, which are tougher to make than germanium PFETs.

Also on tap is an invited paper on nanowires by Harvard professor Charles Lieber, winner of the 2001 Feynman Prize for nanotechnology. Lieber will discuss the growth of single-crystal nanowires.

- David Lammers

EE Times





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