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NSC announces availability of 18-bit LVDS serdes

Posted: 02 Oct 2003 ?? ?Print Version ?Bookmark and Share

Keywords:national semiconductor? low voltage differential signaling serializer/deserializer? lvds serdes? ds92lv18? ds92lv18 design guide and evaluation board?

National Semiconductor Corp. (NSC) has released what it claims is the industry's first low voltage differential signaling (LVDS) 18-bit serializer/deserializer (serdes) to simplify the design of communications systems and to drive down engineering costs.

Suitable for networking and communication system applications such as 3G basestations, wireless local loop systems, broadband access equipment, and high-speed industrial links, the DS92LV18 handles a full 18-bit payload.

Two extra bits can be useful to system designers. Though data buses are typically byte-oriented, many buses also include other non-data signals such as control, parity, frame, and status. Transmitting this non-data information traditionally requires adding another serdes link in parallel or inserting control words or packets into the serial data stream. Both of these methods complicate system design, increasing system cost, and design time.

With the DS92LV18, system designers can serialize their extra signals together with their data at the existing system data bus clock frequency to eliminate the overhead and hassles of previous solutions.

Other features include a "plug and go" synchronization capability, and 15MHz to 66MHz operating range that supports 0.270Gbps to 1.188Gbps payloads. Offered in an 80-pin PQFP package, the product is priced at $9.95 each in 1,000-unit quantities. The DS92LV18 Design Guide and Evaluation Board are also available.

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