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IEEE approves ALF, synthesis standards

Posted: 09 Oct 2003 ?? ?Print Version ?Bookmark and Share

Keywords:ieee? eda tool? advanced library format? alf? verilog?

Paving the way for greater library and EDA tool interoperability, the IEEE has approved Accellera's Advanced Library Format (ALF) and Verilog and VHDL synthesis subsets as new standards. Meanwhile, IEEE 1076-2002 VHDL adds new features to that language.

ALF, approved as IEEE 1603-2003, provides a standard language and semantic representation for design libraries. It supports RTL to GDSII descriptions of functional, electrical performance, and layout views for libraries ranging from cells to complex hierarchical blocks. According to a recent EEdesign tutorial, ALF promises chip designers more control over libraries.

The IEEE 1603 standardization is "a great move forward for nanometer design," said Dennis Brophy, Accellera chairman. "The IEEE [standard] makes a solid target that tool suppliers and data creators are going to be able to hit. It sends a signal that ALF is ready for mainstream deployment," he said.

The Verilog and VHDL RTL synthesis standards have passed balloting as IEEE 1076.6-1999 and IEEE 1364.1-2002, respectively. "Now we have fully ratified synthesis subsets for VHDL and Verilog in place," Brophy said. "This is a way of ensuring that RTL code can be exchanged in different design tools, not just synthesis."

Brophy noted that these are multi-layer standards that consist, at their base levels, of the Synopsys synthesis subsets that are already the de-facto industry standard. But higher levels bring in more functionality, he said. "Not all tools will support that, but we have a solid base that will allow the future exploration of synthesis technology," he said.

IEEE 1076-2002 VHDL, meanwhile, has added three enhancements. First, the definition of concatenation and real types is aimed at improving tool portability. Secondly, VHDL now supports multi-byte characters within comments, which allows documentation in Asian languages. Finally, buffer mode ports have been improved so they can be easily used with "out" or "in-out" mode ports.

IEEE 1076 (VHDL) and IEEE 1364 (Verilog) documentation is available through the IEEE. A draft of the ALF IEEE 1603 documentation is available at the Accellera working group web site.

- Richard Goering

EE Times

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