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Cadence pledges backing for SystemVerilog

Posted: 10 Oct 2003 ?? ?Print Version ?Bookmark and Share

Keywords:cadence design? systemverilog? ic design?

Cadence Design Systems Inc. has announced its support for SystemVerilog. According to the company, they are committed to accelerating the process of bringing SystemVerilog from a specification to a fully implemented international standard.

During the next weeks, Cadence is expected to roll out plans for SystemVerilog support in its Incisive verification and Encounter digital IC design platforms, as well as plans for smoothing the path of SystemVerilog through the Accellera and IEEE standards process.

To date, Cadence has donated and opened up more than a dozen major proprietary languages and formats to the industry, including Verilog, GDSII and SDF.

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