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Altera co-processor supports 3GPP HSDPA standard

Posted: 10 Oct 2003 ?? ?Print Version ?Bookmark and Share

Keywords:altera? turbo encoder co-processor? megacore? cyclone? texas instruments?

Altera Corp. has introduced what it claims is the industry's most cost-effective turbo encoder co-processor available to support the established 14.4Mbps data throughput standard for wireless data applications. Designers can implement the turbo encoder MegaCore function using the company's Cyclone device family for as little as $7.

The turbo encoder implementation is supported by a reference design using a Texas Instruments TMS320C6000 digital signal processor. The reference design simplifies the development flow by enabling the software designer to communicate from the digital signal processor to the co-processor through a basic set of application programmer interfaces.

The latest version of the 3GPP (3rd Generation Partnership Project) wireless standard, v5, added a high-speed downlink packet access (HSDPA) channel to enable an increase in data transfer rates from 2Mbps to 14.4Mbps.

Turbo is a forward error correction scheme frequently used to facilitate reliable and accurate wireless transfer of data from basestations to cellphones. It adds a code unto data prior to transmission that allows the receiving station to detect and correct any errors that may have occurred during transmission.

Craig Lytle, VP of IP business unit, said, "Our turbo co-processor facilitates the integration of software and hardware during system development, thereby reducing development costs, and speeding time-to-market. As a result, major basestation vendors are working with our solution as they develop technologies to meet the new 3GPP requirements."

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