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CPU-monitoring loop eyes system power

Posted: 16 Oct 2003 ?? ?Print Version ?Bookmark and Share

Keywords:cpu? power management? system power? soc? apc?

Traditional approaches to portable power management have focused solely on power delivery. But with the efficiencies of power-management ICs reaching 95 percent, further improvements in battery life based on regulator efficiency can seem minuscule.

A system-level approach to power management, however, demands industry-wide collaboration and standardization. Such collaboration does not come easy; it requires companies to change business models and reach out across the boundaries, even if it means collaborating with competitors.

In November 2002, National Semiconductor and ARM Ltd started an industry-wide collaboration in power management by announcing a relationship based on system-level energy-management solutions. National unveiled a solution called PowerWise technology, while ARM unveiled its Intelligent Energy Manager (IEM) technology, designed to reduce power consumption for ARM-powered SoC devices.

IEM reduces the performance level of the processor without allowing applications to miss their deadlines. Here, the primary challenge lies in predicting the right level of performance for the application. The IEM software and hardware monitor the execution and communication characteristics of workloads, predict the performance levels required and set the performance of the processor to the level that minimizes energy use while still meeting the application deadlines.

The ARM core, for example, has four selectable performance levels, each corresponding to a clock frequency. The more tasks you can perform with a slower clock, the more you conserve battery life - and IEM is good at matching tasks to the lowest clock frequency.

PowerWise technology embeds closed-loop systems in which the power-consuming and the delivery systems operate in close cooperation. Its goal is to cut the demands on the power source while providing peak energy efficiency. An energy-estimation approach calls for several classes of PowerWise monitors, each designed to control the consumption of various subsystems of the mobile phone. Thus, the ARM-National partnership will introduce several devices and methodologies for mobile-phone embedded processors.

Processors are designed to operate reliably over a wide range of temperature levels and silicon process variations. Large safety margins are used to ensure a large safe-operating range at the cost of reduced power efficiency. Just as IEM performance-setting algorithms optimize power consumption based on workload variations, PowerWise devices ensure that the processor does not have to operate under worst-case assumptions, by tuning operating parameters based on temporal environmental conditions.

The heart of the PowerWise technology for embedded processors is a 3,000-gate synthesizable digital core called the adaptive power controller (APC). This accurately monitors the power consumed by the processor and tracks the temperature and device-to-device process variations. The intelligence in the APC is communicated to an external energy-management unit over the 2-wire PowerWise interface.

The APC works in a closed-loop system to reduce the supply voltage of the processor without sacrificing operational stability by monitoring the margin between expected and actual operating conditions. It also receives performance requests from ARM's IEM technology and provides closed-loop adaptive voltage scaling (AVS).

AVS offers improved performance and ease of implementation over existing open-loop dynamic voltage-scaling (DVS) schemes. Using the inherent characteristics of the APC, AVS scales the supply voltage to the absolute minimum required for any given device and for any operating condition, all without any processor intervention.

Existing proprietary open-loop DVS schemes allow the processor to set the supply voltage based on a lookup table of voltage/frequency pairs. The table must be developed based on extensive device characterization to ensure adequate safety margins for all operating conditions and process corners. The closed-loop AVS technology eliminates the need to maintain such a table and the related characterization, as the APC compensates for process corners and variations in operating conditions.

In closed-loop AVS, the APC, together with the PowerWise Interface-compliant energy-management unit provide the fastest possible response time and coordinate all the clock-switching activities. When switching from a lower to a higher frequency, the APC inherently ensures that the supply voltage is high enough to support the new frequency. The synthesizable nature of APC makes it process-independent and transportable.

- Ravi Ambatipudi

National Semiconductor Corp.

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