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SoCMosaic speeds IC co-development

Posted: 16 Oct 2003 ?? ?Print Version ?Bookmark and Share

Keywords:socmosaic platform? toshiba? sonic? emulation platform? whiteeagle systems technology?

Having reduced chip development time with its SoCMosaic platform, Toshiba Corp. is promising to shorten time-to-market further for custom chips by offering a design environment that lets hardware and software development take place in parallel.

Consisting of a programming and debugging environment, emulation system and co-verification tools, the approach cuts six months to a year off software development, enabling an eight-month concept-to-silicon development cycle, Toshiba said.

Structured-ASIC suppliers also claim to slash development time, but they force customers to make design compromises and don't save much cost in the long run, asserted Richard Tobias, VP of the ASIC and foundry business at Toshiba America Electronic Components Inc.

"The NREs for structured arrays are lower by a couple of hundred thousand dollars, but the engineering time and cost will be similar to any other type of ASIC approach," Tobias said. "With SoCMosaic you still pay the full mask cost, but we've reduced the risk and shortened the cycle so much that it makes up for the slightly more expensive masks."

Soft IP

SoCMosaic is a soft-intellectual-property approach that relies heavily on FPGAs and fast I/Os in an emulation environment. Sonics Inc.'s Open Core Protocol-based IP backplane acts as the on-chip bus. The custom-chip platform is offered for 0.18?m and 0.13?m designs in any volume and makes financial sense for designs starting at 20,000 units per year, Tobias said.

Toshiba said its hardware/software co-development environment lets software development begin within a day of an SoC concept's definition. Working from the customer definition of the chip, Toshiba provides an RTL model that can be plugged in to the co-development environment. The environment lets programmers work with various SoC simulation modes while preserving the same programming interface from start to finish. Software can be run on a functional model, a mixed-function/RTL model and an FPGA emulator that runs at 10 percent of the clock speed of the final chip, up to 40MHz.

The emulation platform is WhiteEagle Systems Technology's SwordFish Emulation System, a hardware box with an expandable emulation engine and a wide-bandwidth host interface. Customizable I/O interface cards are included, as are design automation tools and host application software.

Toshiba tapped Mentor Graphics Corp. for co-verification that links software development and debug with logic simulation to deliver co-verification before hardware prototypes are ready. Planned additions are system-level architectural simulation tools; a debug environment; high-level C models; and tools for better optimization of area, power, and speed.

License fees for the Toshiba development environment vary with project complexity. The Mentor and WhiteEagle products are available from those vendors.

- Crista Souza

EE Times





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