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Researcher calls for new HDL approach for SoCs

Posted: 21 Oct 2003 ?? ?Print Version ?Bookmark and Share

Keywords:soc design? international conference on hardware/software co-design and system synthesis? codes+isss? vhdl? verilog synthesis?

A new approach to hardware design languages is needed in order to create a better "programmer's view" for SoC designs, according to a paper delivered at the first International Conference on Hardware/Software Co-design and System Synthesis (CODES+ISSS), held this month in Newport Beach, California.

Thirty papers presented at CODES+ISSS 2003 examined the latest developments in system-level hardware and embedded software design. The conference was created by the merger of two international symposia, each of which had been held for more than a decade. In addition to 30 selected papers, the IEEE/ACM-sponsored conference also included four invited talks, three panels and a keynote speech by Irwin Jacobs, the chairman and chief executive officer of Qualcomm Inc.

With her paper titled "Programmer's Views of SoCs," JoAnn Paul, a research scientist with the electrical and computer engineering department of Carnegie Mellon University, drew an "honorable mention" by audience acclaim. The paper was part of a "work in progress" session, at which IBM researchers described a system for early analysis of SoC devices. Elsewhere at the conference, presenters from the Offis research institute in Germany called for an extended SystemC synthesizable subset.

The conference's best-paper award went to presenters from the University of California at Irvine who outlined a way to generate fast instruction set architecture (ISA) simulators from compact architectural descriptions. The best-presentation award went to researchers from Linkoping University in Sweden who spoke about mixed time-triggered and event-triggered task models for scheduling task execution.

Paul's paper argued that current HDLs do not allow designers to think in terms of systems-on-chip in which not only individual processing elements (PEs), but the entire chip, can be considered programmable-including the network that supports information exchange. What's needed, she said, are new modeling primitives that can capture the trade-offs among data flow, control flow, global states and distributed states.

Paul argued that current, data flow-oriented approaches to SoC design are organized only around computation and communication, and limit the view of the SoC as an embedded, reactive system. Without a system-wide view of control, she said, these approaches don't capture the rich set of possibilities that occur when the SoC is viewed as a programmable entity.

Even SystemC, she noted, is basically an HDL extension that doesn't include the needed primitives for a broader programmer's view.Paul proposed that future design languages include modeling primitives that evaluate trade-offs of control vs. data flow across a number of PEs; select a fixed set of PEs to be considered as a programmable collection; examine trade-offs between global and local states; customize the on-chip network protocol; distinguish system state from computation state; and allow the system state to reside in the programmable network as well as intellectual-property blocks.

A final proposed modeling primitive allows architectural views for coordinating system state and control flow across a finite number of PEs. The approach supports distributed control flow and multipath control.

Researchers from the Offis institute had a more specific focus with a paper that proposed an extended SystemC synthesis subset. The subset is intended to allow better support for object-oriented programming.

While SystemC's C++ orientation makes it an object-oriented language, existing synthesis tools only support a subset that is equivalent to RTL and behavioral VHDL and Verilog synthesis subsets, the presenters noted. The paper argued for additions to SystemC that would provide object-oriented constructs in a way that would better suit the requirements for hardware synthesis.

The proposed extended synthesis subset includes most of the class-related language constructs provided by C++. It also proposes "tagged objects" that support polymorphism, and global objects as an alternative to SystemC channels.

The Odette synthesizer, a prototype tool developed under the European Odette project, uses this extended subset. While many CODES+ISSS papers came from academia, presenters from IBM's T.J. Watson Research Center detailed the System for Early Analysis of SoCs (SEAS), a methodology for front-end design and analysis. The approach uses IP characterization data in conjunction with tools for performance, floorplanning, timing and power analyses, and it is able to analyze the results in an integrated manner, presenters said.

SEAS lets the designer create a block diagram-like description and then run various analyses. For example, the designer could run performance analysis and make any necessary architectural changes. The modified design then could be fed to a floor planner that would estimate chip die size and global routing. Further changes could be evaluated with timing and power analysis.

Presenters described experimental results using a platform-based design built around the PowerPC 405 CPU, CoreConnect bus architecture and IBM's Blue Logic core library. Here, SEAS showed that a higher-performance version of the same design would fit in the same die size, with the same silicon cost. The presenters concluded that SEAS estimates were accurate enough to guide early design decisions.

System design case studies presented at CODES+ISSS included the design of cryptographic co-processors, a reconfigurable fast parallel Solomon decoder and a speech recognition system for handheld devices. In an invited session on "best practices," Mark Underseth, chief executive officer of S2 Technologies, argued for "extreme programming" principles in making software for wireless handsets.

Meanwhile, Faraydon Karim, a fellow at STMicroelectronics, described a number of architectural advances for on-chip multiprocessing.

- Richard Goering

EE Times

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