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Mentor launches 'scalable' verification platform

Posted: 29 Oct 2003 ?? ?Print Version ?Bookmark and Share

Keywords:verification platform? mentor graphics? verilog? matlab? simulink?

Armed with new technologies supporting design-for-verification, Mentor Graphics Corp. has rolled out its Scalable Verification platform. With it, Mentor claims to be first with full Verilog 2001 support, transaction-level testbench generation for emulation, and an HDL link to Matlab and Simulink from The Mathworks.

"We now have scalability and performance where we didn't have that before," said Robert Hum, VP and GM of Mentor's design, verification and test division. Mentor verification users, he noted, can now work at a number of abstraction levels, starting with algorithmic design in Matlab and working down to Seamless hardware/software co-verification, VStation emulation, and ModelSim HDL simulation.

ModelSim v5.8, which is due to ship in November, adds Mentor's first support for Accellera's SystemVerilog 3.1 standard. This support encompasses what Hum called "productivity features," including literals, user-defined types, enumerated data types, structures and unions, dynamic arrays, port connections, and interfaces.

ModelSim 5.8 also claims full support for SystemVerilog's predecessor, Verilog 2001. Many Verilog users have noted that vendor implementation of this IEEE standard has been spotty. "To our knowledge this is the first time Verilog 2001 has been completely supported," said Hum.

The tool does not yet include SystemVerilog 3.1 assertions, but those will come next year, Hum said. Meanwhile, ModelSim 5.8 adds a built-in "assertion engine" that works with Accellera's Property Specification Language (PSL) v1.0. This engine monitors assertions to see if they fire or don't fire, and reports back to the designer through a graphical user interface.

"PSL and SystemVerilog 3.1 semantics are identical, but the syntax is a little different," Hum noted. "We chose to compile PSL syntax. We will compile SystemVerilog 3.1, but it's not out yet."

- Richard Goering

EE Times

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