Aldec, Celoxica offer C-based FPGA design

Providing a mixed HDL and C-based tool suite for FPGA designers, Aldec Inc. and Celoxica Ltd have announced Active-HDL+C. The offering combines Aldec's Active-HDL design entry and simulation with Celoxica's DK engine for C language synthesis and co-simulation.

The package lets designers mix HDL with Celoxica's Handel-C language in one integrated environment. Designers can implement functional specifications at the algorithmic level, and then synthesize directly to an FPGA, the companies claim.

Active-HDL+C provides block-based design entry for VHDL, Verilog, and Handel-C. It then performs co-simulation of these blocks in a single screen. With Celoxica's simulation and synthesis technology, users can simulate C with HDL and compile software algorithms directly into an FPGA from Actel, Altera or Xilinx. The package also offers timing simulation.

Active-HDL+C is available now through both Aldec and Celoxica sales channels. Pricing begins at $35,000 for a single seat perpetual license.

- Richard Goering

EE Times