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Formal tool adds hierarchical PSL support

Posted: 10 Nov 2003 ?? ?Print Version ?Bookmark and Share

Keywords:accellera? property specification language? psl? safelogic? verifier?

Claiming to offer complete verification layer support for Accellera's Property Specification Language (PSL), Swedish EDA vendor Safelogic has announced v1.5 of its Verifier product. The new offering enables hierarchical verification and claims to ease verification re-use through inheritance.

The Safelogic Verifier verifies RTL properties, and tracks bugs without requiring test vectors. It claims to be extremely simple to use. Designers import files, add the corresponding properties and push the "verify" button.

With its enhanced property-based methodology, Verifier 1.5 claims higher performance and increased usability. The new version offers a built-in property viewer that provides early feedback and simplifies debugging.

Safelogic also sells Monitor, a plug-in tool for property simulation. When first announced in October 2002, both tools were based on a proprietary language, but the company has since moved to PSL support. To expand its activities, Safelogic raised $3.5M in second-round venture funding last month.

- Richard Goering

EE Times

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