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Cadence reveals plans for SystemVerilog support

Posted: 14 Nov 2003 ?? ?Print Version ?Bookmark and Share

Keywords:cadence design? systemverilog? eda? accellera?

Cadence Design Systems has revealed plans to support synthesizable SystemVerilog constructs in the April 2004 release of its products, and to support the "bulk" of SystemVerilog by the end of 2004. It's the first timetable offered by Cadence since the company belatedly endorsed SystemVerilog in October.

Until recently, Cadence had cast a skeptical eye on SystemVerilog, which is heavily backed by its arch rival Synopsys Inc. and has not yet been submitted to the IEEE for standardization. But the current SystemVerilog 3.1 is an Accellera standard, and a number of EDA vendors have outlined plans to support it.

Now Cadence is joining that list. "We're supporting SystemVerilog," said Victor Berman, Cadence's recently appointed group director of language and IP standardization. "Our view is that this is the process the industry has chosen to move forward with next-generation Verilog."

Berman said Cadence will support the synthesizable portion of SystemVerilog in an April release of its Incisive verification platform and Encounter implementation platform. The support will include the NC-Verilog simulator and RTL Compiler synthesis tool. Most of the synthesizable subset is in the previous SystemVerilog 3.0, although there are a few additional extensions in SystemVerilog 3.1, Berman noted.

Beyond that, Berman said, Cadence will "aggressively" talk to customers and get feedback on which portions of SystemVerilog to prioritize next. He said Cadence expects to support the "bulk" of the language in a September or October release. "I wouldn't say absolutely everything will be complete," he said. "I'd say there are still some areas that need refinement."

When Cadence announced its initial support for SystemVerilog in October, Berman indicated the company would not support the entire 3.1 specification and did not consider it final. Berman now says Cadence will support SystemVerilog "as it emerges from Accellera."

"The current spec is 3.1. We're working to support that and also to refine it," he said. "There are some constructs that are not uniform across the language. There are no major disconnects, just things we'd like to see improved."

Accellera is in the process of getting user feedback on SystemVerilog 3.1, and is planning on submitting version 3.1a, which may have some slight revisions, to the IEEE 1364 working group before next year's Design Automation Conference in June.

Cadence has already donated technology to the IEEE 1364 working group that may overlap with some of SystemVerilog's assertion and testbench constructs. "The underlying [Cadence] technology is pretty easy to transfer to the final syntax that will come out of Accellera," Berman said.

Berman also noted that Cadence currently supports Accellera's Property Specification Language (PSL) with its VHDL and SystemC tools, and is working to "align" PSL with SystemVerilog.

- Richard Goering

EE Times





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