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Startup tackles system architecture

Posted: 01 Dec 2003 ?? ?Print Version ?Bookmark and Share

Keywords:visualsim? simulation? toolset? performance analysis? arm?

Mirabilis Design Inc., a two-year-old system-level design startup, is quietly shipping a toolset for performance analysis and architectural exploration. VisualSim uses the Ptolemy simulation kernel from the University of California at Berkeley, and Mirabilis calls the product the first commercial offering to combine DSP, analog, protocols and digital architecture in a single simulation.

"We found there was an overarching need in the systems-engineering space for a tool focused on architects and performance engineers, as opposed to the implementation flow," said Deepak Shankar, Mirabilis' founder and CEO. "The goal is to allow architects to spend time designing better products, as opposed to trying to focus on implementation."

Mirabilis began shipping a beta version of VisualSim in late 2002 and started production shipments this year, but has made no public announcements. The toolset is aimed at companies in consumer electronics, communications, semiconductors and defense, as well as research labs.

VisualSim is a graphical tool that can be used for performance trade-off analyses using such metrics as bandwidth utilization, application response time and buffer requirements. It can be used for architectural analysis of algorithms, components, software instructions and hardware/software partitioning, the company said.

VisualSim could, for example, be used to analyze a CPU prefetch and memory bus controller for software tasks; evaluate the performance merits between ARM and MIPS processors; order the instructions on a DSP to meet performance and power constraints; and determine the queuing delay created by adding an extra pipeline stage.

Ptolemy simulation

Shankar, previously a product-marketing manager and business development manager for Cadence Design Systems' Alta group, observed that most commercial system-level tools focus on behavioral design for DSPs. "Currently there isn't a product focused on performance analysis that addresses the conceptual phase, and there isn't really a product that does architectural trade-offs at the system level," he said. "We combine these into a single product."

"We have the libraries to do the performance modeling, and then we have libraries for protocols, networks, DSP, analog," Shankar said. "We have a methodology called dynamic mapping that allows you to connect these behaviors to architectures." He noted, however, that the current release of VisualSim focuses on algorithmic validation, not algorithm development.

Some of the product's versatility stems from its use of the Ptolemy simulation kernel, which supports a variety of models of computation. The rest of VisualSim was developed by Mirabilis, Shankar said. The privately funded startup has nine employees, eight of them engineers.

To do a system specification with VisualSim, designers create a graphical block diagram using elements from Mirabilis' SmartBlocks libraries. These include hardware/software elements of such items as processors, memories, pipelines, buses and DMAs. They also include a networking library of protocol stacks, nodes, routes and network layers. Users can define their own blocks with C/C++ or Java code. For software estimation, users can import C code within a wrapper.

Once a model is created, users can examine data flows at different parts of the system, and use VisualSim to generate statistics. During simulation, users can dynamically view the system activity and accumulated statistical results.

"The Verilog designer, or the embedded-software designer, has the ability to understand the intent and specification from the system-level model we provide, and utilize that to write their code," Shankar said. VisualSim can generate test vectors for use in downstream debugging.

VisualSim is available on Unix, Linux and Windows platforms. A one-year license starts at $15,000.

- Richard Goering

EE Times





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