Toshiba designer takes path of upward mobility

Delving into 'new transistor technology' is all in a day's work for Shinichi Takagi

Takagi became an adept researcher early, while a graduate student at the University of Tokyo studying carrier transport in indium phosphide MOSFETs. Fortunately or unfortunately, his advisor was serving as dean of engineering then, and had little time for Takagi's thesis.

"I had a lot of troubles with my research, but it taught me how to manage myself, to think of things on my own. I know now it was a good experience, to work on the fabrication, on measurements and calculations, and to learn how to do simulations. It gave me the whole image, and helped me become a researcher," he said.

That experience also prepared the 28-year-old, fresh out of school with a Ph.D. in electronic engineering, for his work as one of the new recruits to Toshiba's semiconductor research laboratory in Tokyo. His boss asked Takagi to test a theory of universal mobility that had been proposed by Bell Labs. The goal was to test whether a universal relationship did exist between carrier mobility in the inversion layer and the effective field applied to the device.

"There was no systematic and comparative data, available then," he recalled. So he set to work testing devices to see if carrier mobility was a function of the effective field, independent of the surface impurity concentrations and substrate bias.

The instruments used to measure the device capacitance and current were well known to him from his graduate-school days. That experience also served as good preparation for the work he is doing today as the group leader of the "new transistor technology" research effort at the Mirai semiconductor technology project of Japan's nationally funded Association of Super-advanced Electronics Technologies. His group measures the performance of FETs made of Ge, or strained silicon on silicon-on-insulator (SOI) materials.

Over the past 30 years, CMOS circuit designers have learned to deal with the now-familiar differences between the relatively slow "holes" that serve as carriers in the valence band used in silicon PFETs, and the higher mobility seen with electrons used in NFET devices.

Speed differences

With strained-silicon channels, a thin layer of pure silicon is grown on top of a SiGe alloy, which in turn can be on top of a thick insulating layer. The larger Ge atoms create a tensile strain on the top silicon lattice. These early strained silicon on SOI structures are far too imbalanced. Though Intel researchers claim they have solved the problem (without saying how), most researchers believe that photon scattering in the Ge alloy and other phenomena result in an imbalance: The holes do not gain much from all the work of building a strained-silicon channel, while the electrons profit enormously.

To counter that, Takagi and his co-workers have created devices on silicon with a 110-crystal orientation, rather than the conventional 100-silicon lattice substrates.

The results are startlingly fast PFETs, with hole drain currents in the 110-orientation silicon that are twice as fast as in strained-silicon devices made in the conventional 100 silicon. Unfortunately, the fly in the 110-silicon ointment is less than optimum improvement in electron mobility. But the strained-SOI electron mobility is still higher than the "universal" mobility for bulk CMOS devices.

Takagi heads another Mirai research project, which considers what happens when strained-SOI devices operate at 100°C, a typical operating temperature for MPUs, as compared with room temperature operation of 25°C. Researchers have sought to build devices on ultrathin layers of strained silicon, in part to deal with short-channel effects. But the downside has been a surprising degradation in carrier mobility for devices created in strained-silicon channels less than 10nm thick.

When the devices operate at 100°C, however, the mobility degradation lessens (improves) in the ultrathin silicon channels and becomes about equal to the mobility of 25nm-thick strained silicon. Takagi's team theorizes that at the higher operating temperatures, mobility degradation from quantum-mechanical confinement and interface charge trapping is less significant than at room temperature. Scattering in the Ge alloy also plays a role, one that demands further study, he said.

If Takagi's independent efforts at the University of Tokyo contradict the widely held view that Japanese students blindly follow along in a rote-learning educational system, he is different from "the typical Japanese" in several other respects as well.

Fluent English

In a Japanese culture where few men become truly fluent in foreign languages, Takagi has managed to learn English well.

That effort started in earnest from his first year at Toshiba, which paid for private English lessons for its researchers. When Takagi was notified that he would be giving a paper at the 1988 International Electron Devices Meeting in San Francisco, his co-workers helped hone his writing. He practiced his delivery in English "many times," because "I was scared. It was my first time to attend an international research conference. I had never been abroad before, and the only chance I had to speak English was with Indian graduate students at the university."

In 1992, Takagi got another lucky break. Toshiba arranged for him to spend a year at Stanford University, where Judy Hoyt, then at Stanford and now teaching at the Massachusetts Institute of Technology, was engaged in pioneering research into mobility enhancements in strained silicon.

Takagi joined with graduate students Ken Rim and Jeff Welser, both of whom are now leading players in the strained-silicon device development program at IBM's research center in East Fishkill, New York.

U.S. move?

Takagi, a thin person with the pale complexion of one who spends too much time under fluorescent lighting, said his interest in his work is so intense that it led to the breakup of his marriage shortly before he went to study at Stanford. There were no communication problems per se: his wife was, and still is, a Toshiba semiconductor researcher like himself. To this day, he says, they remain "good friends; we even have dinner together sometimes."

But the couple soon realized that Takagi's interest in device physics was overwhelming any chance of leading a normal married life, even in a Japanese culture once known to be tolerant of long work hours by the male side of the marital equation.

Might Takagi, like several of Japan's most talented professional baseball players now playing for U.S. major league teams, move to the United States?

He doesn't deflect the question, answering that he is "pretty open" to the idea but has never been offered a job abroad. Most Japanese firms, he said, now expect that their researchers will move on by age 50 or 55, most often to university jobs.

Then there is the problem that for most Japanese companies, their interests lie in SoC products that do not require strained silicon or SOI. So it is largely American companies that must take early advantage of strained silicon, SOI and other mobility-enhancing technologies.

"There are good and bad aspects to the restructuring that is happening in Japanese companies. One thing is that many people are retiring early. And while some companies are divesting their semiconductor operations and choosing to concentrate on other product lines as their particular centers of excellence, for Toshiba, the decision has been made to focus on semiconductors. That of course is good for researchers like me," Takagi said.

- David Lammers

EE Times