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Mentor get "physical" with FPGA synthesis

Posted: 08 Dec 2003 ?? ?Print Version ?Bookmark and Share

Keywords:mentor graphics? rtl and physical fpga synthesis solution? precision physical synthesis?

Mentor Graphics Corp. will roll out what it calls the first "integrated" RTL and physical FPGA synthesis solution, aimed at high-capacity devices. With both automatic and interactive modes, Precision Physical Synthesis uses a single data model to bring register-transfer-level source code to placed gates.

Physical synthesis is well-established for ASICs but is just now emerging for FPGAs as those devices grow more complex, said Jeff Wilson, product-marketing manager for Precision Physical Synthesis. A year from now, he said, some FPGAs may have a billion transistors, and interconnects may account for as much as 90 percent of the total delay on some designs. Further, he noted, physical location is critical in FPGAs. Delays are highly dependent on how devices are packed into clusters, such as Xilinx Inc.'s Combinational Logic Blocks. Since logic synthesis does not have this placement information, he said, it's at a big disadvantage.

"When people are just trying to use logic synthesis, we see them going through 30, 40 or 50 iterations just to hit timing," Wilson said.

Under the hood, Precision Physical Synthesis isn't actually a placement tool. It synthesizes to gates, then lets Xilinx or Altera tools do initial placement. It then optimizes a netlist based on the placement information and passes an improved netlist and placement back to the vendor tools. As a result, the vendor tools don't throw away anything that's done by the synthesis tool, Mentor said.

Precision Physical Synthesis is aimed specifically at high-end FPGAs, including the Xilinx Virtex II-Pro, Virtex-II, Virtex-E, Spartan 3 and Spartan 2e. Altera Corp.'s Stratix will be supported early next year, Mentor said, and its Stratix GX and Cyclone will be supported in a beta release in early 2004.

Gary Smith, chief EDA analyst at Gartner Dataquest, said Mentor is acting wisely by targeting these high-end FPGAs and the "power users" who design with them. These customers don't expect free vendor tools, Smith said, and work with budgets more in line with low-end ASIC tool costs.

What Mentor brings to the party, said Wilson, is a single data model and a product that can handle both RTL and physical synthesis. That includes an accurate physical model based on the FPGA vendor's design rules, he said. "We understand the vendor's placement rules, so that when we do retiming or replication, we're assigning specific locations and locking elements down," he said. "When we pack things, we have to make sure things are legal."

Precision Physical Synthesis can run in a "pushbutton" mode. Here, users simply input VHDL or Verilog RTL code, along with timing constraints and physical constraints. What comes out, after the initial placement is brought back in from the FPGA vendor tool, is a placed netlist.

An incremental mode can provide an additional performance boost. The tool includes PreciseTime, an incremental timing analyzer, and PreciseView, an interactive graphical environment with which users can fix a coding problem and change constraints or the physical implementation. "Suppose you have a multiplier in a non-optimal location," said Peter Suaris, chief scientist for Mentor's FPGA synthesis group. "The timing analyzer will show the critical path and will color instances based on the slack, so it's easy to see that if you move the multiplier, you'll fix the timing problem."

With the purely automated flow, Wilson said, users are seeing a 15 to 20 percent gain in device performance vs. logic synthesis. "With interactive editing, the sky is the limit in what you can do," he said.

Mentor Graphics claims to have a unique algorithm for retiming. That technique moves registers across combinational elements to meet timing constraints. The tool can also reposition and replicate registers to push them closer to a destination.

In a recent user review at the E-Mail Synopsys Users Group, an anonymous engineer said he was unable to meet timing after three months of manually driven optimization using a competitive tool.

However, after three days of configuration work with Mentor's tool and one 38-minute run, he was able to produce a design in which all of the routes met timing. He noted, however, that Mentor's physical synthesis is still an iterative process. "You still have to synthesize, place and route, then use Precision Physical to tweak timing, then place and route again," he wrote.

Precision Physical Synthesis is available now on Windows NT, Solaris, Linux and HP-UX starting at $35,000.

- Richard Goering

EE Times





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