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Tower Semiconductor standardizes on TriCN interface IP

Posted: 10 Dec 2003 ?? ?Print Version ?Bookmark and Share

Keywords:tower semiconductor? tricn? i/o library? chips? ic designs?

IC wafer-manufacturing foundry Tower Semiconductor has selected TriCN's base I/O library and a suite of interface IP for use in their 0.18&3181;m process. Tower will make this IP available to customers designing high-performance chips for production at its Fab 2 facility.

TriCN's base I/O library is a comprehensive set of cells containing all elements required to produce a pad ring, allowing developers to create the interface foundation for their IC designs. The base I/O library is specifically geared to support designers developing high-speed applications. Additionally, the company's interface specific I/Os (ISI/Os) are tuned toward particular high-performance interface applications such as memory, networking and graphics.

"We're standardizing on TriCN technology for our interface IP needs because of their distinguished track record developing high-performance interfaces," said Sergio Kusevitzky, V.P. of IP and Design Services with Tower Semiconductor. "Furthermore, the flexibility of their Base I/O library allows customers with a wide range of design applications to successfully develop chips with minimal risk. We believe this is a key benefit for customers designing next-generation ICs for production in our fab."





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