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Tool set eyes process test-chip design

Posted: 10 Dec 2003 ?? ?Print Version ?Bookmark and Share

Keywords:silicon canvas? test-chip development? laker t1?

Silicon Canvas Inc. will release a platform for process test-chip development that the company calls the first commercial product of its kind. The Laker T1 platform is designed to help foundries and integrated device manufacturers create test chips to verify, optimize and calibrate new silicon processes.

While test-chip development is an essential part of process development, it isn't easy, according to Silicon Canvas. The cycle can take two years and may involve three to six respins. But Laker T1 can shorten this process to eight months or less with zero or one respin, the company said.

"In the traditional flow, it takes time to regenerate the test structures," said Hau-Yung Chen, president of Silicon Canvas. "Most foundries use the manual creation method to deliver their test chips."

The Laker T1 product is based on Silicon Canvas' Laker, an automated full-custom layout solution for analog, mixed-signal and system-on-chip designs. Laker is a connectivity-driven editor that understands design rules, the company said. Laker T1 supports several types of process test chips. Lithography test chips, for example, are used for equipment tuning and optimization, early drive run experiments, optical proximity correction (OPC) and critical-dimension control.

Technology-development test chips are used for design rules, Spice modeling, reliability and yield analysis, and process integration. Library test chips are used for process qualification, yield analysis, interconnect modeling, design kit preparation and OPC.

Inputs to Laker T1 include a matrix of test structures; a design constraint file for probing card information, test structure placement and wiring information; and a test structure library and probing pads. The program also takes GDSII layout files and Tcl/Tk library files.

Richard Goering

EE Times





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