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STMicro flash chip with low pin count architecture

Posted: 12 Dec 2003 ?? ?Print Version ?Bookmark and Share

Keywords:stmicroelectronics? firmware hub? fwh? flash memory? m50flw?

STMicroelectronics has introduced what it claims is the first two-in-one Firmware Hub (FWH) and Low Pin Count (LPC) Flash memory for storing BIOS content in a wide range of PC desktops, laptops and servers.

The M50FLW product line is designed for Intel or non-Intel chipsets and combines both Firmware Hub and Low Pin Count architectures on the same chip. As the FWH and LPC protocols are both based on the same overall format, the product can configure itself in either FWH mode or LPC mode by decoding the first 4 bits received during the START time slot. From the values of the 4 bits, the M50FLW defines in which mode, either LPC or FWH, further data will be decoded. It also supports full decoding of the instruction set defined in LPC mode and in FWH mode.

With an auto-detection circuitry that automatically distinguishes the bus type (FWH or LPC), the M50FLW family is Read compatible to Intel 82802 Firmware Hub devices and conforms to Intel LPC Interface Specification Revision 1.1.

The first product, M50FLW040, is a 4Mb device operating from a 3V to 3.6V single supply voltage. The device features 8 blocks of 64KB, including 5 blocks of 64KB each and 3 blocks subdivided into 16 uniform sectors of 4KB each. Two options are available on the three blocks - M50FLW040A is offered with 2 blocks at the top and one at the bottom and M50FLW040B has one block at the top and two at the bottom.

The M50FLW040 fits into the PLCC32 package as well as the TSOP40 (10-by-20mm).

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