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0-In Design tacks on static verification capability

Posted: 17 Dec 2003 ?? ?Print Version ?Bookmark and Share

Keywords:0-in design automation? verification tool suite? verilog 2001? systemverilog? accellera?

The latest release of 0-In Design Automation Inc.'s assertion-based verification tool suite lets users run a design through debugging prior to simulation, potentially bringing the debug tools into the design cycle much earlier. With v2.1, the company has also added new assertion checkers and protocol monitors, plus support for SystemVerilog constructs.

The new static verification flow involves two tools in the assertion-based verification (ABV) suite: 0-In Checklist and 0-In Confirm. Checklist performs a range of automatic RTL checks. Confirm performs an exhaustive analysis on assertions, reporting when assertions are proven and providing counterexamples when they are not.

Before v2.1 was available, designers had to provide a simulation state to start Confirm, said Richard Ho, senior architect at 0-In. That meant at least some simulation had to be run. Now, however, Confirm can provide both proofs and counterexamples statically, without simulation.

"Now you can use the power of model checking even before a testbench environment is set up," Ho said. "You can also find design bugs much earlier in the design process."

Confirm still requires initial states from which to begin its analyses, but users can now provide those in a simple textual format, Ho said.

Meanwhile, v2.1 enhances the 0-In CheckerWare library with three new checkers, bringing the total to more than 70. One is a "mutex" (mutual-exclusion) checker that makes sure multiple signals aren't active at the same time. Others are "always" and "never" checkers that can probe whether a property is always, or never, true.

With the new release, 0-In has added more support for the Verilog 2001 standard, although Ho acknowledged that it doesn't encompass the entire language yet. 0-In has also added support for design constructs in SystemVerilog, with SystemVerilog 3.1 assertions to follow in the second half of 2004. The release also adds initial support for Accellera's Property Specification Language.

0-In also has made new entries to its CheckerWare library, adding two monitors for standard interconnects. One is the company's first offering aimed at storage products-a monitor for serial attached SCSI (SAS). Another is an upgrade of the PCI-X CheckerWare monitor that conforms to the recently announced 2.0 version of the standard.

CheckerWare monitors are used during simulation or emulation to warn users of protocol violations. They generate structural coverage and transaction statistics that can be analyzed using the company's ABV tool suite. A total of 25 monitors are available from 0-In today.

Version 2.1 of the ABV Suite is available now. The PCI-X 2.0 and SAS CheckerWare monitors are available now for $35,000 each for a one-year license.

- Richard Goering

EE Times





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