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Tool promises parallelizing synthesis

Posted: 23 Dec 2003 ?? ?Print Version ?Bookmark and Share

Keywords:center for embedded computer systems? university of california? spark? synthesis tool?

Touting a new approach to parallelizing, high-level synthesis, the Center for Embedded Computer Systems at the University of California at Irvine has released its Spark synthesis tool to engineers. Available as a free download, Spark takes C-language input and produces register-transfer-level VHDL code.

Spark uses parallelizing compiler technology previously developed for instruction-level parallelism, and "re-instruments" it for synthesis by adding mutual exclusivity of operations, resource sharing and hardware cost models. According to researchers, the tool yields high-quality results, especially for control-intensive microprocessor functional blocks and multimedia and image-processing applications.

"We believe that this is a new enabling technology that will finally fulfill the promise of high-level behavioral synthesis," said Sumit Gupta, research specialist at the Center for Embedded Computer Systems. "Spark is a prototype that demonstrates that this technology can be successfully used to produce a high quality of results."

In a paper at this year's International Conference on VLSI Design, Gupta and his colleagues claimed that experiments run on MPEG-1 and Gimp image-processing applications showed that Spark allowed improvements of up to 70 percent in performance, without any increase in the overall area or critical path of the final synthesized designs.

Behavioral synthesis has never really caught on among chip designers. "High-level synthesis has gotten a bad rap despite the claims over two decades. It rarely delivered in terms of expectations on quality of synthesis results," Gupta said. "We are looking to provide a solution that improves the state of the art by bringing a new range of code transformations to high-level synthesis."

Spark differs from previous attempts at behavioral synthesis in two ways, Gupta said. First, it offers more techniques to improve the quality of results. Second, it's not a pushbutton tool; instead, it gives designers control over the transformations applied to the design, so they can experiment with different optimizations.

Spark takes purely behavioral C code, although it offers a language-independent approach that could easily be adapted to SystemC or SystemVerilog, Gupta said. Following pre-synthesis optimizations, it uses a "toolbox" approach that offers various kinds of code transformations and heuristics. With user input, Spark does scheduling, allocation, resource binding, control synthesis and back-end code generation.

The tool uses an intermediate representation that retains all of the information given in the input description. Spark converts C input into a control-data flow graph, and then synthesizes it into an architecture consisting of a data path, memory, control unit and interconnections. "We have gone out of the box of traditional high-level synthesis and developed ways in which the source code is moved through the control flow even as we are carrying out individual synthesis tasks," said Gupta.

Gupta acknowledged that Spark is a prototype, and that it hasn't been used in a production chip design flow. He said, however, that there have been several inquiries from commercial companies interested in licensing the technology.

The Center for Embedded Computer Systems is currently offering free downloads of Spark for Linux and Solaris platforms, along with a user manual, a tutorial and an MPEG-1 player design example.

- Richard Goering

EE Times

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