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Xilinx, IBM assure of serdes interoperability

Posted: 26 Dec 2003 ?? ?Print Version ?Bookmark and Share

Keywords:xilinx? ibm? serdes? transceivers? fpga?

Xilinx Inc. has announced successful interoperability testing of the IBM high-speed serdes (HSS) core with Xilinx's Virtex-II Pro 3.125 serial transceivers. With Xilinx FPGAs and IBM ASICs often on the same boards, the interoperability testing significantly reduces overall product time-to-market by allowing customers to focus on design issues rather than verifying electrical compliance.

Applications now enabled include high-speed interface requirements for Fibre Channel, PCI Express, Serial Rapid I/O, Serial ATA, Serial Attached SCSI, 10Gb Ethernet and OIF interfaces.

The test and verification interoperability plan was designed to ensure full and rigorous electrical interoperability testing of the two cores. Both SERDES technologies were tested interactively for transmit and receive functions. Additionally, the signaling was performed asynchronously in order to most faithfully reproduce an actual functional environment. A variety of pseudorandom test patterns were used in order to mimic actual data traffic. Furthermore, both backplane and point-to-point signaling were characterized. In the end, no bit errors were logged between the two devices in any of the test cases.





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