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EDA startup offers graphical Verilog tool

Posted: 05 Jan 2004 ?? ?Print Version ?Bookmark and Share

Keywords:hdl? orion consulting? visual rtl? verilog code? e-mail synopsys user?s group?

Aiming to simplify HDL code development and documentation, Orion Consulting Inc. has rolled out Visual RTL, a tool that generates synthesizable Verilog code from graphical logic-block schematics. The three-person company is shifting away from consulting to focus on the new product.

With Visual RTL, said Art Gmurowski, founder of Orion Consulting, designers no longer have to type in text. "It's far simpler to enter a design graphically," he said. "This gives you the benefit of having the design documented, and also the ability to generate error-free code. You don't have to consider low-level coding issues."

There are other products that generate HDL code from graphics, but Visual RTL has unique features that provide more support for "lower-level design," Gmurowski said. He noted, for example, that when users place gates, the input pins to the gates will adjust automatically. Nets are drawn automatically when components are connected or moved.

The product makes use of color-coding, and one example is the color-coding of registers based on their clock domains. Visual RTL also adjusts the widths and inputs of components dynamically, and can adjust the width of busses and wires as components are added. A library provides various logic components, including registers, muxes, counters, logic gates and truth tables.

Input to Visual RTL can be a mix of graphics and code, Gmurowski noted. Users can put down an "assign" statement block if there's an element that isn't in the library. The output is synthesizable Verilog code. Compared to hand coding, he noted, Visual RTL eliminates the need to use sensitivity lists.

As noted in a recent E-Mail Synopsys User's Group (ESNUG) bulletin, Visual RTL competes with a similarly-named product from Summit Design, Visual Elite. John Cooley, ESNUG moderator, commented that he didn't see much difference between Visual RTL and Visual Elite.

But Rami Rachamim, Summit director of marketing, noted that Visual Elite supports not just Verilog, but also C/C++, SystemC and VHDL, along with SystemVerilog next year. Visual Elite, he said, is a platform that supports functional modeling, design and verification.

"Startups need to focus on innovation and new technologies for solving users' problems, rather than duplicating features and names in an established market," Rachamim said.

Gmurowski, who said he has not used the Summit product, said Visual RTL was developed independently and provides a "unique solution."

Visual RTL is available now on Linux, Solaris and Windows platforms for $7,500 per license. A free demo is available at Orion's website.

- Richard Goering

EE Times





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