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0-In assertion compiler is multilingual

Posted: 01 Jan 2004 ?? ?Print Version ?Bookmark and Share

Keywords:0-in? multilingual? translator? abv? psl?

Claiming to offer a "universal translator" for assertions, 0-In Design Automation announced an enhanced assertion compiler for its ABV tool suite. It reads assertions in multiple formats and outputs synthesizable Verilog.

0-In's assertion compiler reads assertions from the company's CheckerWare library, IEEE 1364 Verilog and the Open Verification Library. In the coming months, it will add support for Accellera's PSL and SystemVerilog 3.1, the company said. The resulting Verilog assertions can be read by any Verilog-compatible tool, including simulators, formal verifiers, emulators or FPGA prototyping systems.

However, the compiler is not a standalone tool; it comes with any of the tools in 0-In's ABV suite, such as 0-In Check, which manages assertions in simulation and provides management tools. "What we've seen in large SoC and ASIC designs is that people are using third-party blocks from IP vendors," said Richard Ho, 0-In's chief architect. "They might have different assertion formats in them. There's a need to use all those assertions in verification."

Output isn't limited to 0-In tools, he said. "The compiler generates a synthesizable Verilog version of the assertions and from there it goes anywhere, kind of a universal translator for assertions." In the 0-In press announcement, third-party vendors including Cadence Design Systems, Novas Software and Verisity endorsed 0-In's support for different assertion formats.

Far from giving something up in translation, Ho said, the assertion compiler actually adds value to assertions. For example, it adds coverage capability to PSL and SystemVerilog assertions. That supports the "unified structural coverage" features within the ABV suite, such as structural coverage, simulation structural coverage and formal structural coverage.

Further, Ho said, the compiler adds a management capability so that users can see all the assertions throughout the hierarchy, even if they're in different formats. "A project manager can look at what parts of the design don't have enough assertions," he said.

- Richard Goering

EE Times

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