Verification platform for Jeda language rolls

Bringing to market a new approach to verification, startup Jeda Technologies released Jeda-X, a commercial product based on the Jeda hardware verification language. An earlier version of Jeda, created by one of the company's founders, is available on an open-source basis.

Jeda-X provides an enhanced version of the language and a methodology guide. It's touted as being an intuitive, easy-to-use verification "platform" that facilitates design reuse, allows hardware/software co-simulation and lets engineers work at a higher level of abstraction.

Jeda was developed by Atsushi Kasuya, Jeda Technologies' CTO, who created the language while he was a verification engineer at Juniper Networks. Kasuya was an original developer of the Vera language and is the author of two Vera patents. Jeda became an open-source language in 2001.

While the open-source version is still available, Jeda-X is a licensed, supported commercial product that has been tested and used by customers, said Eugene Zhang, president of Jeda Technologies. He noted that there have been a number of bug fixes and some language enhancements, as well as third-party interfaces. For example, Jeda-X can generate testbenches for simulators such as Cadence Design Systems' NC-Verilog, Mentor Graphics' ModelSim and Synopsys' VCS.

Jeda Technologies faces a tough challenge in competing with established hardware verification languages such as Vera and "e," not to mention SystemVerilog 3.1, which incorporates many testbench development features based on Vera. But Zhang said the company is confident it has a competitive solution.

One feature that stands out, Zhang said, is the language's aspect-oriented programming features. This allows functions across classes to be added or replaced without modifying the original code, making it possible for features such as debugging or performance measurements to be turned on or off.

Jeda Technologies, in fact, donated some key elements of its technology to the IEEE 1364 committee in consideration for the upcoming Verilog 2005 standard. In addition to aspect-oriented programming, these include object-oriented programming support for writing testbenches, enhanced list and array data types for behavioral modeling, concurrent programming support, synchronization primitives for multithreaded execution and cycle-based testbench support.

Jeda-X also promises a constrained random-stimulus generation, a compiled engine for fast simulation execution, a Perl-like regular expression engine, multiprecision arithmetic operations, an easy mechanism for user-defined extensions and an automatic garbage collection to avoid memory leaks. Further, Zhang said, Jeda-X is a scalable solution that can work at a chip or block level.

It's currently unknown which technology donations will end up in Verilog 2005, which most observers expect will encompass SystemVerilog 3.1. "If the industry has the consensus to reach a standard, we are 100 percent behind that standard," said Zhang. "Our belief is that the eventual standard has to come out of the IEEE."

Meanwhile, Zhang said, Jeda Technologies has a product that people can use to tape out chips today, while the next Verilog standard may not be sorted out for another two years. In fact, he said, Jeda has already been used by Juniper Technologies to tape out terabit and gigabit router chipsets.

In addition to Juniper, public customer endorsements for Jeda-X have come from wireless-IC provider Spreadtrum Communications, multimedia company Exavio, consumer electronics chipset provider Legend Silicon, Tsinghau University in China and the China Shenzhen IC center.

- Richard Goering

EE Times