Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

Sequence wins power, inductance patents

Posted: 06 Jan 2004 ?? ?Print Version ?Bookmark and Share

Keywords:sequence design? rtl power analysis? gate-level libraries?

Adding to its patent portfolio, Sequence Design has been awarded U.S. patents for RTL power analysis and extraction of parasitic mutual inductance. Technology described in the patents has been integrated into Sequence products.

U.S. patent 6,598,209, "RTL power analysis using gate-level cell power models," lets users estimate power at the register-transfer level using standard gate-level libraries. The author is Sergei Sokolov, Sequence principal engineer. Sequence has incorporated this technology into PowerTheather, a tool for RTL and gate-level power estimation.

U.S. patent 6,643,831, "Method and system for extraction of parasitic interconnect impedance including inductance," describes a method in which parasitic impedances, including inductance, can be extracted for an IC to allow more accurate modeling and timing analysis.

The patent's authors are K.J. Chang, professor at Taiwan's National Tsing Hua University; Li-Fu Chang and Rob Mathews of Sequence; and Martin Walker, founder of Frequency Technology. The new patent complements a former Sequence patent on inductance extraction methods. Technology from both patents has been incorporated into Columbus-AMS, a 3D RLCK extractor for mixed-signal, analog, memory and full-custom digital designs.

- Richard Goering

EE Times





Article Comments - Sequence wins power, inductance pate...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top