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Study eyes pickup in design and EDA

Posted: 08 Jan 2004 ?? ?Print Version ?Bookmark and Share

Keywords:eda tools? verification? signal integrity?

Design activity is likely to pick up this year, with a corresponding increase in demand for EDA tools, according to a new study released by RBC Capital Markets. The study also found that most chip designers will stay at 130nm this year.

Authored by analysts Garo Toomajanian and Debra Otto, the study surveyed electronic design engineers and engineering team managers. Additional responses came from CAD tool managers. Consumer electronics and communications were the most active sectors.

According to the study, ASIC and FPGA designers intend to move to higher gate counts in 2004. Almost half of ASIC and FPGA designs are expected to be 5 million gates or more.

As of now, approximately 46 percent of those surveyed are working on designs with less than 2 million gates, 29 percent are working on designs with 2 to 5 million gates and 14 percent are working on 5 to 10 million gate designs. The remainder is working on designs with at least 10 million gates.

The move to 90nm is slow, however. Only 4 percent of respondents are working on 90nm designs now, but 21 percent think their next design will be at 90nm.

The study authors predicted that the EDA industry could see revenue growth of 5 to 10 percent in 2004, with the growth weighted towards the second half of the year and momentum carrying into 2005. While Synopsys and Cadence remain the primary vendors of the respondents surveyed, users said they expected increased tool usage from other vendors as well.

The study also found that design closure, verification and signal integrity remain the top concerns for chip designers.

- Richard Goering

EE Times





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