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Transaction-level emulation platform rolls out

Posted: 08 Jan 2004 ?? ?Print Version ?Bookmark and Share

Keywords:emulation and verification engineering sa? fpga? zaiq technologies? verification platform? eve?

Emulation and Verification Engineering SA, a provider of FPGA-based emulation boards, and Zaiq Technologies Inc., a developer of verification intellectual property, are teaming up to announce a transaction-level verification platform. Based on EVE's ZeBu platform, the system will include Zaiq software and will offer a 1,000x to 100,000x speedup over software-based simulation, the partners said.

The system uses transactors, or transaction-based models, from Zaiq's SystemWare Verification Component (SVC) library. Zaiq software also supports testbench generation as well as a C-to-HDL interface.

Zaiq announced a similar partnership with Aptix Corp. in September. In both cases, Zaiq is using Accellera's new Standard Co-Emulation Application Programming Interface (SCE-API) to bring transaction-level modeling to a hardware verification platform.

Lauro Rizzatti, CEO of U.S. operations for EVE, said transaction-level modeling is an order of magnitude faster than the cycle-based emulation offered by the company's ZeBu platform, which by itself is many times faster than software-based simulation. Further, he said, transaction-level modeling simplifies testbench creation, allowing designers to think in terms of transactions rather than cycles or events.

"ZeBu technology was designed to support transactors, but until now the users had to write their own transactors or engage with a consultant," Rizzatti said. Aimed at providing a low-cost alternative to conventional emulators, ZeBu boards provide a capacity of up to 12 million ASIC gates and offer execution speeds of up to 12MHz.

Overlay on hardware

Rich McAndrew, executive VP at Zaiq, said his company used the SCE-API to come up with a synthesizable bus-functional model that lets the user transfer and control entire transactions. The company's transactors include this model, along with a C-language function that provides an API for the test writer. Zaiq offers transactors for protocols such as Ethernet, SPI, PCI, PCI-X, USB and Amba.

"We overlay our technology, which is standard and portable, on top of the EVE hardware," McAndrew said. "You can move an entire packet or DMA [direct memory access] transfer into the emulator." The companies claim that the technology enables electronic system-level verification. Zaiq also offers an environment designed to help users create and organize transaction-level tests, as well as a TestBench Plus transport layer, which communicates test information between C and VHDL or Verilog. It supports threads so concurrent tasks can be initiated.

Language options

Because the transactors support a C-language API, McAndrew noted, users could write their system-level tests in another language such as Vera or "e." But mixing transactions and events would be difficult, he said.

EVE introduced its ZeBu ZV-8000 verification boards in March. The boards use Virtex FGPAs from Xilinx Inc. A single board offers 1.5 million ASIC gates and up to eight boards can be connected for a 12 million-gate capacity.

Pricing for the combined ZeBu/SVC system starts at $66,000, and the offering is available now.

"The thing that's attractive about EVE is that they represent a breakthrough in emulation technology," said Zaiq's McAndrews. "All of a sudden this stuff is starting to become available to the masses, with an entry point under $100,000. This should appeal to everyone in the world who's producing chips."

Authors from Zaiq and EVE offer a tutorial on evaluating emulation performance in an EEdesign exclusive feature.

- Richard Goering

EE Times





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