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EDA/IP??

Tanner adds design tool

Posted: 14 Jan 2004 ?? ?Print Version ?Bookmark and Share

Keywords:tanner da? hiper verify? hiper? l-edit? mentor graphic?

Providing a low-cost alternative for IC design rule checking (DRC), Tanner EDA has introduced HiPer Verify, the first product in the company's new HiPer line of layout and verification products. The new product offers hierarchical, foundry-compatible DRC for analog and mixed-signal chips.

The new HiPer line provides higher performance than the company's existing L-Edit products, said Nicholas Williams, product manager at Tanner EDA. But it will still offer a significant cost savings compared to tools from big EDA vendors, he said. Like L-Edit, the HiPer line is Windows-based and is aimed at full-custom chips with significant analog or mixed-signal content.

As a full-chip, hierarchical DRC product, HiPer Verify could complement or potentially replace products such as Mentor Graphic's Calibre or Cadence Design Systems' Dracula, Williams said. But it doesn't have the performance or capacity of those products, he acknowledged, and it's not aimed at digital ASICs. Tanner claims that HiPer has run successfully on chips with up to 620,000 equivalent gates.

What it does offer is cost savings. HiPer Verify "tops out" at around $30,000 with all the options, Williams said. Thus, he said, it may complement the more expensive DRC programs by allowing customers to have some HiPer Verify licenses for their smaller chips.

HiPer Verify offers "foundry-compatible" DRC, allowing users to run Calibre or Dracula rule files unmodified, directly from the foundry. This eliminates the need to set up DRC rules manually. It also supports "background DRC," allowing users to run design rule checking in the background while working on chip layouts.

A command file editor allows syntax checking of DRC commands. A DRC error navigator takes users directly to the area of a design where an error occurs.

HiPer Verify is available now. It requires Tanner's L-Edit DRC product, but does not require that L-Edit is used to lay out the chip.

- Richard Goering

EE Times





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