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Two IP vendors pave the road to low power

Posted: 21 Jan 2004 ?? ?Print Version ?Bookmark and Share

Keywords:low-power ic? eda tool? ic design?

The push for low-power ICs in advanced processes has produced little consensus beyond the notion that no single fix will do. Designers can no longer get by with just reducing voltage and, in designs at 130nm and below, two kinds of leakage compound the difficulty of using energy efficiently: subthreshold leakage through a channel and gate leakage through a gate dielectric.

Solutions require the cooperation of device designers, EDA tool designers and chip architects, with no one party holding the magic bullet. That truth is apparent with this week's scheduled announcement of two products that aim to support advanced low-power design techniques: a low-power 130nm logic library from Virtual Silicon Inc. and a six-transistor SRAM compiler from Monolithic System Technology Inc. (MoSys).

The Virtual Silicon library is designed to ease the implementation of a "power islands" design approach that separates a chip into modules operating at different voltages. Each module's voltage is set at the minimum necessary to meet its performance requirements.

"This is a technique that has been developed inside very large design teams as a proprietary approach, by piecing together things they had and could develop for themselves," said Barry Hoberman, president and CEO of Virtual Silicon. "We are offering this library, based on the standard 130nm TSMC (Taiwan Semiconductor Manufacturing Co. Ltd) process, so that ordinary design teams can use the technique as well."

The VIP Powersaver library includes special elements necessary for the power islands approach, explained vice president of marketing John Ford. There are cells to isolate voltage regions from each other and to perform level shifting for signals passing between islands; flip-flops that consume about half the power of their standard compatriots; and clock-gating cells. There are also more-subtle elements, such as circuits to provide the supply voltages to the level shifters that are not readily apparent from the surface.

All of these cells are implemented in a standard TSMC logic process, and do not rely on TSMC's special low-leakage process. "We've found that many design teams are avoiding the special process," said Mark-Eric Jones, vice president and general manager for intellectual property (IP) at MoSys. "It does an excellent job of reducing leakage, but at a cost of nearly twice the dynamic power of the high-speed process."

The Powersaver library, which is deliverable now, is the first step in Virtual Silicon's road map, Hoberman said. Many other aspects of design have to be addressed as well to achieve low power at these geometries. Some, such as memory compilers and EDA tools, will come via relationships. Others, more susceptible to Virtual's internal circuit design expertise, will be addressed through new product lines.

The first example of the relationship strategy is the coordinated announcement from MoSys. The company, known for its 1T SRAM IP, is announcing a compiler for 6T SRAM, a product to help attack the power problem.

"We have already announced the 1T-SRAM-mobile technology to reduce the leakage current from our 1T arrays by about three-quarters," said Jones. "But the 1T arrays are only optimal for relatively large memories-half a megabit or more. Our customers have been asking if we could apply the technology we developed for controlling leakage to smaller memory arrays."

MoSys started the 6T effort with TSMC's standard 6T SRAM cell. "It is already optimized for the process and would be hard to improve in terms of area or performance," Jones said. The company then added technology developed for the 1T architecture: internal biasing techniques that use the standard TSMC cell design but improve the leakage, and optimizations of the sense amps and peripheral circuitry that surround the array. The result is over 50 percent reduction in leakage, MoSys said.

MoSys also made macro-level changes. Instead of developing a separate 8T cell for dual-port SRAM, it used the multiplexing strategy used in the 1T arrays to get full dual-port functionality-without blockages but at a slightly lower performance than single-port-using the 6T cell. The company found that combining the optimized 6T cell with peripheral circuitry for dual-port functionality was actually denser than using less-optimal 8T cells.

On-the-fly correction

Just as important, MoSys added its transparent on-the-fly error-correction circuitry to the SRAM compiler, so that at a designer's discretion even small 6T SRAM arrays can have error protection. This not only slashes soft-error rates to under 10 FiT/megabit, but eliminates the need for redundant cells, laser trimming or electrical switching to preserve yields.

The Virtual Silicon and MoSys announcements are synchronized not only in time but in technology-the libraries and the SRAM compiler have been tuned to interoperate. But that is just the beginning of the relationships the companies are weaving to give design teams a seamless approach to low-leakage design.

At the tool level, the companies are working closely with Synopsys Inc. to make sure that its tools can take advantage of the new libraries and use the multiple views necessary to see the characterization of the cells at all their different voltage points. Similarly, Virtual Silicon is working with National Semiconductor Corp.'s PowerWise initiative at the architectural level, and is reportedly also cooperating with some of the IP and platform design houses involved in PowerWise.

"None of these techniques is new," Hoberman said. "They all have been available here and there to the best-funded, strongest design teams. What we are trying to do is to pull all the fingers together and give design teams a hand, so to speak-to pull all these ideas into one place and put them into a standard flow for a standard process."

- Ron Wilson

EE Times





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