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Configurable logic device merges ASIC, FPGA features

Posted: 26 Jan 2004 ?? ?Print Version ?Bookmark and Share

Keywords:gladiator? asic? fpga? cld?

Phillips: Gladiator offers
the flexibility of FPGAs
and efficiency of ASICs.

FPGA's flexibility and quick design cycle and ASIC's low cost and power consumption are evident in Leopard Logic's recently released Gladiator configurable logic device (CLD).

According to Leopard Logic Inc. Gladiator is the industry's first in configurable implementation platform where users can benefit from on-the-spot design change with FPGAs, at the same time incorporating the efficient fixed-block ASIC logic on the design.

The Gladiator CLD offers lower nonrecurring engineering (NRE) costs by eliminating vendor-driven back-end processing. This, and its in-field-programmability, can make Gladiator a suitable choice for access/edge networking, SAN and wireless infrastructure products with a need for short-term cost-effective FPGA and ASIC solutions.

"The current approach to future-proof system designs is to combine FPGAs with off-shelf components and ASICs," said Warren Miller, vice president for marketing of Avnet Cilicon. The ASIC and FPGA merger in a single device eliminates separate glue devices and this would extend product lifetime and market scope while offering the best trade-off in terms of cost, performance and time-to-market.

The Gladiator CLD provides customers with a faster turnaround time in order of weeks instead of months compared to traditional ASICs, and uses a low-cost tool chain that allows rapid design and manufacturing cycles.

Gladiator CLD also implements a certain amount of high-speed logic in the mask-programmable (MP) segment of the device. The CLD can be further customized with the use of a field-programmable (FP) fabric that allows reprogrammability by simply downloading a new bit stream into the device, allowing instant in-field upgrades.

ASIC and FPGA functionality is achieved in the CLD with a combination of Leopard Logic's proprietary Hyperblox FP and MP fabrics. Hyperblox FP is a hierarchical, mux-based point-to-point interconnect fabric, which enables speed, predictability and reliability better than legacy FPGA. Hyperblox MP uses the same logic core cell architecture as the Hyperblox FP with single-layer via-mask replacing the SRAM configuration. These fabrics share a unified core cell architecture allowing simple partitioning and full automation.

Filling the gap

According to Chris Phillips, president and CEO of Leopard Logic, customers are often caught in a dilemma where FPGAs can't meet power requirements, while ASICs can't be an option because of long lead times, high risk and lack of flexibility. "By combining the flexibility of FPGAs with the efficiency of ASICs, Gladiator is the ideal choice for customers caught in the gap. With system speeds of 500MHz, high-performance memories and I/Os, and good DSP performance in a single-chip, Gladiator addresses today's most pressing market needs." Phillips said.

The rigid partitioning and bandwidth bottleneck between devices at board level limits the system performance of devices that combines ASICs and discrete FPGAs on a PCB. Gladiator CLD implements the integration of FPGA fabric on the same chip that facilitates the delivery of increased performance at lower power consumption. Gladiator offers the lowest total cost of ownership because of its shorter design cycle comparable to FPGAs. Research firm In-Stat/MDR forecasts that the market for devices using embedded FPGA technology will skyrocket to $650 million with a CAGR of 115 percent in 2007.

"ASICs just don't work for many companies anymore because of escalating costs and longer development cycles. The FPGA market is profiting from this trend. Over the next several years we see a fast-growing market for hybrid devices that use a combination of hardwired logic and embedded FPGA fabrics," said Jerry Worchel, senior analyst at In-Stat/MDR.

First in the Gladiator CLD family is CLD6400, providing 6.4 million system gates and 680 I/Os with a memory of 2.3MB. At a system speed of 500MHz, it offers 32 giga-multiply-accumulate (GMAC) operations per second DSP capability. It also has 16 on-chip PLLs and DLLs to drive clocks and implement high-speed interfaces with 5W maximum power consumption.

CLD6400 is manufactured in TSMC's 0.13?m CMOS process on 300mm wafers to deliver optimal performance at minimal cost. It is available now and pricing will be $99 in 100,000 unit volumes in early 2005.

- Reden Mateo

Electronic Engineering Times - Asia

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