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Serial storage SoCs demanding to test

Posted: 02 Feb 2004 ?? ?Print Version ?Bookmark and Share

Keywords:soc test? ata? scsi? sata? serial storage soc?

The storage industry last year began widespread implementation of serial-based technologies to replace parallel physical-interface standards (ATA and SCSI) currently used to connect a system bus to disk storage devices. Integrating the serial interface directly in storage SoCs is the natural continuation of a trend to higher integration, but it is not without its own set of challenges in SoC design and production testing.

The advances afforded storage devices that use serial technology are significant. First, data throughput is increased: desktop and mobile disk drives that support, for example, serial ATA (SATA) interfaces can increase speeds from the shared 100MBps (for parallel ATA) to dedicated bandwidth of 150MBps or 300MBps. In addition, serial interface cables are thinner than bulky parallel cables and use fewer pins, saving space inside the box.

This market transition comes at a time when hard disk drive (HDD) manufacturers are under tremendous pressure to keep storage costs at a minimum. In the last few years, manufacturers have begun incorporating mixed-signal storage SoC solutions in their desktop and mobile HDDs. An HDD SoC combines previously discrete read-channel and hard-disk controller electronics and represents the single most important piece of silicon in a drive. This component controls the encoding and decoding of data from a storage platter, the storage and retrieval of data and the speed at which the HDD can access data. The signal integrity enabled by HDD SoCs helps dictate the overall storage capacity of a drive, and innovations in these electronics are driving areal densities to 120GB per platter for desktop drives and 80GB for mobile.

Preserving signal integrity

The benefits inherent in SoC integration - improved board space, reduced power consumption and lower cost - are enhanced with the addition of on-chip high-speed serial interfacing, but design concerns must be addressed to ensure product performance and ease of testing. The read-channel IC within the SoC processes the electrical signals from the drive's preamplifier, so appropriate signal-integrity preservation measures must be taken in the design of, for example, an integrated SATA SoC to ensure that the high-speed signals from the SATA interface do not disturb the operation of the read channel. Likewise, the SATA signal transmitter and receiver are high-performance analog circuits that have to be carefully shielded from electrical noise.

The production volumes for these solutions are massive. A storage semiconductor provider will ship up to 5 million SoCs per month to any given HDD customer. Compounding this challenge is the value that HDD manufacturers place on reducing defective parts per million; a failure rate of even 0.01 percent is unacceptable given the cost and time-to-market consequences of system or field failures.

Adding a native high-speed serial interface to this SoC builds on complex mixed-signal architecture and increases the challenges of silicon testing. The read channel and serial-interface portions of the solution are extremely analog-intensive, requiring a test methodology that must source complicated mathematically generated waveforms, accurately capture responses and then process them using DSP. Juxtaposed against these analog test elements is the hard-disk controller portion, which requires traditional digital ASIC-type defect testing using digital vectors, at speeds that are cutting-edge for most ATE.

One benefit of serial-interface SoC integration is that its low-voltage differential signaling is compatible with advanced semiconductor process technologies. This simplifies design and supports high-volume manufacturing and production testing of storage SoCs, which are developed using 0.13?m CMOS processing.

Multisite SoC testing is imperative to meet the fast time-to-market mentioned earlier and capital expenses in check. Using customized ATE, these serialized SoCs are tested in batches of two or four and employ design-for-test methodologies, in which all segments of this mixed-signal solution (read channel, controller and serial interface functionality) are tested in parallel. In addition, the ATE must provide high-speed test stimulus and data capture as well as simultaneous processing of the output, which will be critical as the industry quickly moves to next-generation 3Gbps parts.

The mechanics of the automated test fixture are also extremely important when testing these high-speed chips. Not only is it critical to get clean, deterministic and broadband signals to the IC under test, but also to ensure good electrical contact with the pads at wafer probe and pins at package test.

Contact resistance, load board characteristics, reflections, impedance match and crosstalk between signals can affect high-bandwidth analog signals used during SoC production testing.

These important matters must be addressed when designing the mechanical interface between the ATE and the probers/handlers and by appropriate design for testability and observability during the design phase of the SoC.

Simply put, no other piece of silicon exists in the electronics industry to match the analog and digital complexity, high-volume requirements and price pressures of HDD SoCs. A high level of mixed-signal design expertise and production testing is required to ensure that SoC quality is not compromised.

However, the reward for proper production-testing efforts is a solution that minimizes the cost and maximizes the performance and reliability of a high-performance HDD.

- John Harris

Sr. Product Manager

Storage Division

Agere Systems Inc.

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