Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Strained SOI on the move to mainstream

Posted: 02 Feb 2004 ?? ?Print Version ?Bookmark and Share

Keywords:soi? strained silicon? system-on-insulator? chip design? silicon on bulk silicon?

Some industry observers have concluded that strained silicon on bulk silicon trumps strained silicon-on-insulator (SOI). Nothing could be further from the truth. The industry road map calls for strained silicon on a SiGe template layer on insulator at the 65nm node in 2007 and strained silicon directly on insulator at the 45nm node, which means that a material supply has to be ready in 2004 to 2005. As always, business strategy dictates the best time of adoption for technology innovations by individual companies.

When you look at the industry, there are those IC makers that remain on top by staying on the leading edge of new technologies. These companies have been the early adopters of SOI, either at 180nm or 130nm. They clearly recognize the advantages of building circuits in silicon over an insulating layer, with higher performance and lower power consumption being the most visible advantages.

For these companies, moving to strained silicon at the 65nm node will give them faster chips, and the transition will be a relatively simple one. It will also be cost-effective, since they have already made the necessary investments in adapting their circuit design and fabrication processes to the SOI environment.

On the other hand, some companies stay on top by focusing on manufacturing excellence, introducing new technologies in small increments that enable them to maintain their sales margins. They only move to a new technology when it is relatively mature and commensurately cost-effective. However, these companies know - and have said as much - that they will need to move to engineered substrates such as strained SOI by the 45nm node.

The advantage of strained silicon lies in its electrical properties. The crystalline lattice of the top, electrically active layer of silicon is strained so that electric charges (electrons and holes) flow faster.

Chips built on wafers with a layer of insulator consist of millions of islands with transistors, each isolated from the other islands and from the bulk-silicon substrate below. The separation of the transistors from each other simplifies circuit design, since the designer doesn't have to devise complex schemes for trench or well formation. Furthermore, the insulating layer protects the active layer of strained silicon from the parasitic effects of the bulk-silicon base. Taken together, these two factors facilitate more-compact VLSI chips and easier CMOS process integration for nodes of 65nm and beyond.

Performance gains with the insulating layer are largely the result of faster transistor switching. If an insulating layer separates the active cap of strained silicon from the bulk-silicon substrate, large-area p-n junctions are replaced by dielectric isolation. The source and drain regions extend down to the buried oxide, reducing the leakage current and junction capacitance. This enables IC makers to fabricate CMOS circuits that dissipate less power in both standby and operating modes. The result is chips that run faster and can operate in a wider temperature range.

Strained SOI chips are also less vulnerable to short-channel effects than strained-silicon chips built on bulk. Short-channel effects are the result of charge sharing between gates and junctions. The gate's electrical field competes with the fields of the source and drain regions. But when a layer of insulator is introduced so that the source and drain regions extend down to the buried oxide, the short-channel effect is greatly reduced or eliminated.

Scaling is a major issue in future technology nodes. The goal is to make smaller and smaller transistors, passing the 25nm barrier at the 65nm technology node. This is a reasonable goal in strained SOI, but not on bulk. In fact, device scaling into the sub-20nm physical gate length regime requires an insulating layer.

Given the physical limits of transistors in bulk silicon, it is clear that the entire high-performance chip industry will eventually be obliged to move to engineered substrates incorporating an insulating layer. Although business decisions will determine the point at which the late adopters of insulated substrates will make the move, in the end, they will do so. It comes down to the laws of physics.

- George Celler

Chief scientist

Soitec Corp.

Article Comments - Strained SOI on the move to mainstre...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top