Scan-based testing can do job

Delay-inducing defects are causing increasing concern in the semiconductor industry today, particularly at the leading-edge 130nm and 90nm nodes. To effectively test for such defects, the at-speed behavior of the logic has to be emulated in the most cost-effective way possible.

Before scan-based structural-test techniques were implemented, functional-pattern testing was the only method employed in manufacturing test. Development cost, difficult debugging and the high cost of test hardware made functional-pattern testing unappealing. As clock rates and design sizes increased, testing using functional patterns became more impractical.

Today, scan-based transition-fault testing techniques are increasingly used to test for such delay-inducing defects. Two popular methods to generate test patterns for scan-based testing are the launch-from-capture technique (broadside delay test) and the launch-from-shift technique (skewed load delay test).

Transition-fault model

According to the transition-fault model, there are two types of faults possible: slow-to-rise and slow-to-fall. A slow-to-rise fault at any node means that the effect of any transition from 0 to 1 (or 1 to 0 for slow-to-fall) will not reach a primary output or scan flip-flop within the given time.

Any test pattern that successfully detects a transition fault comprises a pair of vectors (V1, V2). V1 is the initial vector, which sets a target node to the initial value. V2, the next vector, not only launches the transition at the corresponding node, but also propagates the effect of the transition to a primary output or a scan flip-flop.

In the launch-from-capture technique, the first vector of the pair is scanned into the chain and the second vector is derived as the combinational circuit's response to the first vector.

The steps involved include:

? Shift the data into the scan chain N times;

? Toggle the scan-enable signal and allow the circuit to settle;

? Pulse the clock twice. The first pulse will launch the transition while the second pulse will capture the response.

In the launch-from-shift technique, the first and second vectors of the pair are delivered through the scan cells themselves. If the scan-chain is N bits long, an N-bit vector is loaded by scanning in the first (N-1) bits. The last shift clock is used to launch the transition, followed by a quick capture. The steps involved include:

? Shift the scan chain (N-1) times to obtain the first vector. Apply PI values as required;

? Toggle the scan-enable pin;

? Change the PI values as required;

? Pulse the clock to capture the response into the scan flip-flops.

The key to this step is the capability to change the scan-enable signal at-speed. This change has to happen precisely between the launch and capture pulses.

Methods to reduce cost

Low-cost testers constructed from off-the-shelf components are a promising alternative to expensive ATE. To keep the cost low, timing requirements are relaxed, compared with high-performance testers.

The biggest constraint with transition-fault testing is that there is only one high-speed pin available. However, the tester was designed for transition testing. Since the launch-from-capture technique does not need an at-speed scan-enable signal, it is ideally suited for use on the low-cost tester.

The launch-from-shift technique results in improved test coverage with a fewer number of patterns, in most cases. The main reason is that the launch-from-capture technique is based on a sequential ATPG algorithm, while the launch-from-shift method uses a combinational ATPG algorithm. Commercial pattern generation and compression tools are more efficient in a combinational ATPG environment. However, the results show that we can still achieve a moderate level of coverage by using the launch-from-capture technique on a low-cost tester.

With careful planning, it is possible to achieve high coverages even with the launch-from-capture technique if enough attention is paid during the design stages. A number of trade-offs will have to be made in a low-cost test environment and with careful planning and with execution most of the at-speed test requirements can be met.

- Vinay Jayaram, Jayashree Saxena and Kenneth Butler

ASIC Design for Test Group

Texas Instruments Inc.