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Toolset eyes process test-chip design

Posted: 02 Feb 2004 ?? ?Print Version ?Bookmark and Share

Keywords:silicon? chip? test? opc? optimization?

Silicon Canvas Inc. has released a platform for process test-chip development that the company calls the first commercial product of its kind. The Laker T1 platform is designed to help foundries and integrated device manufacturers create test chips to verify, optimize and calibrate new silicon processes.

While test-chip development is an essential part of process development, it isn't easy, according to Silicon Canvas. The cycle can take two years and may involve three to six respins. But Laker T1 can shorten this process to eight months or less with zero or one respin, the company said.

"In the traditional flow, it takes time to regenerate the test structures," said Hau-Yung Chen, president of Silicon Canvas. "Most foundries use the manual creation method to deliver their test chips."

The Laker T1 product is based on Silicon Canvas' Laker, an automated full-custom layout solution for analog, mixed-signal and SoC designs. Laker is a connectivity-driven editor that understands design rules, the company said. Laker T1 supports several types of process test chips. Lithography test chips, for example, are used for equipment tuning and optimization, early drive run experiments, optical proximity correction (OPC) and critical-dimension control.

Technology-development test chips are used for design rules, SPICE modeling, reliability and yield analysis, as well as process integration. Library test chips are used for process qualification, yield analysis, interconnect modeling, design kit preparation and OPC.

Inputs to Laker T1 include a matrix of test structures; a design constraint file for probing card information, test structure placement and wiring information; and a test structure library and probing pads. The program also takes GDSII layout files and Tcl/Tk library files.

Laker T1 has several modules. The test structure compiler module generates the layout structures that are used to collect process information. It provides a GUI with pattern-creation functions, such as copy, fill, align, array and distance.

The test line manager module creates test lines, which include the probing pads and test structures and the wiring between them. Its test device editor compiles the original test structure library with specific technology rules. A probing-line editor defines the hardware-probing card information, while a test line editor defines the template file for test structure placement and wiring information.

The test line realizer module creates the test line with the desired layout pattern and wiring quality. Users can specify parameter values and orientation of test lines, and automatically route realized test structures with probing pads. Realized test lines are exported as GDSII files. Finally, the program includes an automatic documentation-generation facility.

According to Chen, the cost savings can be enormous. With the cost of a sub-100nm fab currently running $2 billion, he noted, ramping up a process even one day early can save more than $1 million. Laker T1 pricing reflects that reality, with a cost starting at $1 million for a three-year license. "We think it's well-justified with the return on investment that Laker T1 can deliver," Chen said.

- Richard Goering

EE Times





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