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Synopsys, Cadence give nod to SystemVerilog changes

Posted: 02 Feb 2004 ?? ?Print Version ?Bookmark and Share

Keywords:verilog? systemverilog? cadence? accellera? vpi?

The EDA market's largest suppliers have endorsed the Accellera standards organization's efforts to enhance the SystemVerilog hardware description and verification language, saying the changes will lead to better tools and better designs.

The enhancements, which will be based on feedback Accellera has received from vendors and users spotlighting some shortcomings in the current ver 3.1 of the specification, will be implemented in SystemVerilog 3.1a, to be released to the IEEE this year. The two standards organizations have moved forward uneasily, and not in lockstep, to create a single standardized successor to Verilog. Representatives of Accellera outlined the enhancements to SystemVerilog 3.1 at the Accellera SystemVerilog Symposium last year.

Useful process

"Accellera is focusing on making sure it addresses designers' needs," said Victor Berman, group director of language and intellectual property standardization at Cadence Design Systems Inc. Noting that changes are a common part of language standardization, Berman said Cadence "sees the standardization effort as a useful process and will continue to support it."

"The planned, evolutionary enhancements will enable vendors to provide more comprehensive solutions, especially in the areas of verification and tool interoperability, with the new functional-coverage feature and enhanced Verilog Procedural Interface (VPI)," said Steve Smith, senior director of strategic marketing at Synopsys Inc. Smith called ver 3.1 "the strong foundation that enables designers and vendors to start using the new standard." The enhanced version 3.1a "expands on that foundation by adding some new capabilities," he added.

Changes that are expected in SystemVerilog 3.1a include improvements in global declarations and separate compilation, a broader assertion capability, a functional-coverage metric, an extended VPI and semantic consistency with Accellera's Property Specification Language (PSL). Also on tap are technology donations from EDA startup Bluespec Inc., which is developing a high-level synthesis product based on SystemVerilog.

Dennis Brophy, Accellera's chairman, said the purpose of releasing SystemVerilog 3.1 was to get user and vendor feedback. "The users felt we fell short on what should be in the language," he said. "They told us what they needed, and we've done that."

Brophy acknowledged that the planned changes in 3.1a go beyond what was originally expected but said they will result in a better standard. "I think it elevates and improves the automation of verification more significantly than what 3.1 encompassed," he said.

Cadence, which announced first-step support for SystemVerilog November 2003, "will support SystemVerilog across our synthesis, simulation, formal verification and emulation technologies to enable customers to improve the quality and efficiency of chip design and verification," Berman said.

Synopsys, a strong backer and contributor to Accellera's standardization efforts, took the proposed enhancements into account when planning its product support for SystemVerilog, Smith said. "We're on target to roll out comprehensive SystemVerilog support during the coming year across our Galaxy Design and Discovery Verification platforms. Our VCS, design compiler and design checker Leda tools currently support SystemVerilog design features. Additionally, SystemVerilog assertions support is available in VCS. We'll add the new SystemVerilog 3.1a features upon Accellera's ratification."

Vassilios Gerousis, chairman of Accellera's technical committees, told symposium attendees that Accellera plans to release SystemVerilog 3.1a to the IEEE in June this year. He said PSL will follow later in 2004, and Verilog-AMS, a mixed-signal simulation standard, will go to the IEEE in 2005. Accellera's policy, he noted, is to "incubate, refine and solidify" standards before taking them to the IEEE.

David Smith, chairman of Accellera's SystemVerilog testbench extensions committee, said Accellera is working closely with the IEEE 1364 working group to ensure their Verilog standards do not diverge. Both Accellera and the IEEE, he said, are working hard to maintain a consistent Backus-Naur Form - that is, underlying grammatical formalism - between their respective Verilog language efforts.

David Smith said the SystemVerilog 3.1 language reference manual generated more than 200 errata and extensions. In his view, the biggest change in SystemVerilog 3.1a has to do with packages and separate compilation. SystemVerilog 3.1 includes a "root" construct that provides global declarations, he explained, but runs into problems with separate compilation. The upcoming 3.1a reduces the scope of root to its being an unambiguous hierarchical reference. The enhanced specification also adds "packages," which provide globally available declarations in a reusable form, and "compilation units," which are defined to support separate compilation, he said.

Many additions in 3.1a concern testbench generation. Neil Korpusik, co-chairman of the SystemVerilog testbench extensions committee, cited the addition of a functional-coverage metric that helps measure the progress of design verification. Reactive testbenches can be created and can monitor functional coverage during simulation.

Other testbench enhancements for 3.1a include fine-grained process control, random-weighted-case statements, dynamic queuing, built-in methods, stream generation, more effective constraints, virtual interfaces and sequence event control, Korpusik said.

Simple operators

Matt Maidment, a member of Accellera's SystemVerilog design committee, identified two more changes in 3.1a: the extension of memory system tasks to include SystemVerilog data types, and the use of operator overloading to enable the use of simple operators with complex SystemVerilog types.

He also described the two Bluespec donations. Data structures called tagged unions provide type safety and brevity, making it easier to use formal verification. And a technique called pattern matching can make code both concise and expressive, he said.

Swapnajit Mittra, chairman of the SystemVerilog C-interface committee, said 3.1a brings full VPI access to all of SystemVerilog. Further, new extensions to the VPI give full access to waveform files, regardless of file format. "Each vendor will provide a library supporting this API for their format," he said. "As a user, you won't have to modify code; it will be portable from one simulator to another."

Extensions that support assertions were described by Faisal Haque, chairman of the SystemVerilog assertions committee. An "assume" directive lets a user tell the tool to assume a given property is true. Local variable usage is extended. And assertions can be used within functions in a procedural scope.

Harry Foster, who chairs Accellera's formal-verification technology committee, said his group has made progress in aligning SystemVerilog assertions with the PSL formal property language. SystemVerilog assertions are now semantically aligned with PSL, and that the languages don't have different semantics for the same syntax. The next task, Foster said, is to maintain the same syntax for the same semantics.

- Richard Goering and David Roman

EE Times

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