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Teseda, Agilent certify STIL link between DFT, production test

Posted: 20 Feb 2004 ?? ?Print Version ?Bookmark and Share

Keywords:teseda? agilent technologies? design-for-test? production test platforms? ieee 1450?

Teseda Corp. and Agilent Technologies Inc. have announced the first link that ensures transportability of Design-for-Test (DFT) data between engineering and production test platforms, wherein customers of the Teseda V500 and the Agilent 93000 SOC Series can quickly and reliably validate, debug, and apply IEEE 1450 (STIL)-based production test data generated by EDA tools.

The net result is a test development flow that cuts weeks from time-to-money for many semiconductor products. Agilent and Teseda verified STIL transportability between the Agilent 93000 and the Teseda V500 using pattern files created by automatic test pattern generators (ATPGs) from DFT tool vendors, including Synopsys, Mentor Graphics, Cadence, and SynTest.

The STIL files were imported into the two systems and validated as equivalent. Pattern edits were made on the V500 and the revised patterns were output in STIL by the V500 and then read into the Agilent 93000; these patterns were also validated as equivalent. This process is claimed to ensure that DFT tests that run on one system will also run on the other with equivalent results.

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