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EDA execs promote cost savings

Posted: 20 Feb 2004 ?? ?Print Version ?Bookmark and Share

Keywords:moore's law? eda? cadence design systems? synopsys?

Design companies are struggling with cost-performance tradeoffs as they seek to keep pace with and drive Moore's Law, according to a panel of EDA executives.

"We can make [chips] smaller and faster, but can we make them cheaper?" Ray Bingham, CEO of Cadence Design Systems asked the Design Automation and Test Europe conference here on Tuesday (Feb 17, 2004). Increasingly, the innovation required to lower the cost of designing advanced chips is a function of targeting research funds.

Bingham called for greater collaborative R&D among customers, competitors and universities as a way to share costs and promote EDA innovation. Collaborative research "creates the leverage Moore's Law is based on," he said.

Design reuse and the ability to drag and drop large amounts of intellectual property into designs could also cut the cost of advanced chip designs from "tens of millions of dollars to millions of dollars," added Wally Rhines, CEO of Mentor Graphics.

Greater use of automation is also expected to reduce development costs, but the EDA industry model has only been suited to its use for the last 18 months or so, according to Synopsys CEO Aart de Geus. The result has been a productivity payoff that has started the process of reduce design costs, de Geus added.

"It's all about EDA rescuing Moore's Law," the Synopsys chief said.

-George Leopold

EE Times





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