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Processor designers debate faster clocks

Posted: 23 Feb 2004 ?? ?Print Version ?Bookmark and Share

Keywords:sun? intel? amd? fujitsu? ibm?

An evening panel session held at ISSCC here Tuesday (Feb. 17, 2004) debated some of the consequences of clocking processors at multi-GHz rates. Engineers from Sun, Intel, AMD and Fujitsu complained about power consumption, programming issues, and costs.

Philip Emma, manager of systems technology at IBM proclaimed himself the "whipping boy" for high clock speeds. If we examine interconnect flight time, careful to avoid resonance in the wire lengths, we could obtain clock speeds as high as 60GHz, he theorized. But would we need to terminate on chip wires, just to avoid those resonances? Such a device would be a consummate power eater, he concluded. The cost of computing machinery would be a function of the power it consumed, he said, not its clock rate.

Consumer demand for "big iron" would not likely track the rise in clock speeds, advised Alisa Sherer, a technology fellow with Advanced Micro Devices. This meant that marketing dollars would need to track or exceed engineering dollars to ensure that consumers would be enticed by fast clocking PCs, she said.

Multithreading could multiply the amount of work performed by the microprocessor with each clock cycle, said Marc Tremblay, a technology fellow with Sun Microsystems. In principle, a 256-thread machine could achieve terahertz clock rates, with each thread running a GHz race through the machine.

"If threading takes over, the GHz required is much lower," agreed Doug Carmean, a principal architect with Intel Corp. in Hillsboro.

"But no one knows how to program a machine with more than two threads," protested an audience questioner from MIT. And the compiler technology would likely not keep up with the requirements of multithreading, Sun's Tremblay conceded.

But none of the panelists doubted that there would be fabrication processes in place that would support multi-GHz processor designs. (An aggressive roadmap shown at the Intel Developers' Forum, IDF, across the street from ISSCC here, suggested putting technology shifts on a two-year cycle, culminating with a 25nm manufacturing process in 2009-2010). Clock estimates given in response to an audience challenge ranged from 7GHz to 10GHz.

Power consumption, a function of gate fan-out loading within the individual processor's design, would be the limiting factor, reminded Alisa Sherer. Fan out loading on the order of 20 to 22 gates would consume much more power at high clock rates than designs loaded by 16 or 18 gates, she said. Complexity would inevitably favor higher fan out loading.

"We could do 10GHz," Sherer postulated. "But a 5GHz clock was a much better target." Even then, the processor is likely to consume a couple of 100W - and there will be few PC applications likely to support that, she concluded.

- Stephan Ohr

EE Times

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