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Parallel clocking extends chip operating speed

Posted: 23 Feb 2004 ?? ?Print Version ?Bookmark and Share

Keywords:nec? cmos? clock signal? circuit? ip?

NEC researchers have developed a parallel clocking approach for circuits that operate at 10GHz, which is capable of setting clock frequency separately from the operating frequency of a chip. This approach makes it possible to continuously scale up the operating frequency without becoming susceptible to the natural signal degradation and reliability problems usually associated with increasing clock frequencies.

Providing a parallel clocking scheme differs from parallel processing data in that the parallel clocking scheme is applied to the timing and minimizes each "timing drift" in the clock signal throughout the chip. This can lead to larger size system-on-chips.

In a paper delivered at the International Solid State Circuits Conference here on Wednesday (February 18, 2004) NEC researchers detailed how this parallel clocking provides a seamless SoC whose IP cores are synchronized while having different operating frequencies. A chip might have one IP core that is suitable for sequential processing whose operating frequencies was 10GHz and also have four IP cores that are suitable for parallel processing whose operating frequencies are 2.5GHz and are fed from the same clock signals.

The researchers reported on a test chip fabricated in a 0.18?m CMOS process that has clock lines distributed in five sections, each composed of a buffer and 3mm interconnections. Compared to conventional clock distribution the buffers reduce clock skew by 85 percent when 2.5GHz four-phase parallel clocking is used. A multiphase flip-flop circuit is used for the parallel clocking, in a two pulsed-latch and two push-pull configuration.

"NEC believes that as the result of finer wires and ever higher performance future chips will need to implement this technological paradigm shift based on the parallel clock concepts," said Masao Fukuma, vice president of NEC Corp.

"We are confident that we can track the ITRS [International Technology Roadmap for Semiconductors] for the required clock frequency all the way to the 22nm processing node using this phase averaging technique," said Masayuki Mizuno, assistant manager of NEC's Silicon Systems Research Laboratories.

- Nicolas Mokhoff

EE Times

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