Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

Applied makes 65nm X-architecture test chip

Posted: 27 Feb 2004 ?? ?Print Version ?Bookmark and Share

Keywords:applied materials? cadence design systems? test chip? x initiative consortium? x-architecture?

Applied Materials Inc., working with Cadence Design Systems, Inc., has made a 65nm test chip using diagonal as well as traditional right-angle Manhattan interconnects.

The X Initiative consortium said that Applied created the first 65nm X-architecture chip at the company's technology center in Sunnyvale, Calif. Applied fabricated an X-architecture 90nm test chip last summer.

The companies will discuss the challenges involved with the X-architecture in two papers to be presented at the SPIE lithography conference being held in San Jose this week. The X-architecture supports designs with significantly less wire and fewer vias, while improving speed, power, and costs, the consortium said.

The test chips "provides further confirmation of the manufacturing readiness and scalability of X Architecture designs for future process nodes," said John T.C. Lee, GM of Applied Materials' Maydan Technology Center. The approach leverages standard design, verification, mask making, processing, and inspection disciplines, he added.

Cadence provided the test structure design and chip validation tools, and a Canon 193nm scanner was used for the project.

- David Lammers

EE Times





Article Comments - Applied makes 65nm X-architecture te...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top