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Starc to release Starcad-21 design methodology

Posted: 01 Mar 2004 ?? ?Print Version ?Bookmark and Share

Keywords:semiconductor technology academic research center? starc? chip design methodology? starcad-21? rtl?

Using the know-how of its 10 semiconductor member companies, the Semiconductor Technology Academic Research Center (Starc) will release v1 of a chip design methodology named StarCAD-21 this month that covers silicon implementation from RTL to GDSII.

The platform will initially target volume 90nm SoC designs for digital consumer products, and will then be expanded to 65nm designs. A future version planned for release in March 2006 will cut RTL-to-GDSII design time to about a sixth of present levels, the center said. "The deeper a process goes, the more issues such as timing, signal integrity, reliability and productivity come to the surface. These issues . . . are inextricably connected and force designers to make trade-offs. To solve such challenges, we need a design methodology," said Nobuyuki Nishiguchi, senior manager of the design-methodology and intellectual-property reuse engineering group at Starc.

The methodology divides the RTL-to-GDSII design process into three phases - estimation, refinement and implementation - and defines clear criteria at the end of each phase to tell designers whether or not they can go to the next step.

Two hurdles - "prediction and prevention" and "check and go" - must be cleared before advancing a step. The methodology ensures that a design can be implemented in silicon if it passes the signoff criteria at the end of the implementation phase, Starc said. The clear criteria laid out for completing the "check and go" process at each phase will reduce drastically the time needed to finish a design, Nishiguchi said.

"Such criteria also existed in conventional design processes, but they were not clear enough," said Sagoro Hazama, general manager of Starc's design technology development department. "Individual designers' know-how has been covering the ambiguities. But the swelling number of tools needed and rapid technology evolution make it difficult for individuals to handle these design challenges." That is where the StarCAD-21 project steps in, Hazama said.

Japan's leading semiconductor companies established Starc in 1995 for fundamental research in semiconductor technologies. Ten companies at present are shareholders: Fujitsu, Matsushita, NEC Electronics, Oki, Renesas, Rohm, Sanyo, Sharp, Sony and Toshiba. About 30 design engineers from these member companies worked on the StarCAD-21 project.

Starc released a beta version of StarCAD-21 to shareholders in January. Practical chips were designed with the beta version and are being verified at Advanced SoC Platform Corp., a test line venture whose shareholders are the same 10 companies that own Starc. StarCAD-21 v1, incorporating revisions based on the test production, will be released this month to shareholder companies. A design kit will include a chain of recommended tools, design guidelines, criteria for signoffs and handoffs, scripts, evaluation methods of analytical accuracy, and methods for evaluating and handling the libraries supplied by each tool vendor. Each of the shareholders will be able to offer the design platform to its customers.

Starc plans to release v2 in a year, with refined signal integrity and power consumption capabilities. Version 3, with higher design efficiency and an open interface, will be released in March 2006.

Version 1 of the methodology can trim the 72 weeks now needed to complete an SoC to 24 weeks, Starc said. Continued progress with tools will eventually halve that number, the organization believes. The StarCAD-21 team is working with tool vendors such as Cadence Design Systems and Synopsys, Starc said. Nishiguchi said the refinement of individual tools is helpful but does not solve the entire design problem. Comparing each tool to a musical instrument and the design flow to an orchestra, he said StarCAD-21 acts as a conductor to harmonize the total performance.

- Yoshiko Hara

EE Times

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