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Renesas SRAM offers high-level density

Posted: 27 Feb 2004 ?? ?Print Version ?Bookmark and Share

Keywords:Renesas Technology Corp. has announced the development of schemes effective in achieving what it claims as the world's smallest cell size and lower power consumption in dual-port SRAM.?

Renesas Technology Corp. has announced the development of schemes effective in achieving what it claims as the world's smallest cell size and lower power consumption in dual-port SRAM.

The company has also confirmed the efficacy of the developments together with a circuit method that reduces leakage current and operating current while maintaining high-speed capability.

A new memory cell layout structure has been devised, using a shared contact technique whereby a diffusion section and a polysilicon section for wiring, are connected with a single contact. As a result, a dual-port memory cell has been achieved that has the world's smallest memory cell size per bit of 2.04?m?. Normally, the cell size of dual-port SRAM is at least twice that of single-port SRAM of the same design rule, but this technique has produced a cell area to be approximately 1.6 times as large. The structure also provides fully shielded bit lines, making it possible to reduce interference noise due to electrical signal interactions between adjacent wires.

The scheme also features a dynamic "column bias control method" for memory cell array. The previous mainstream method for reducing leakage current has been performing voltage control in block units or in row direction of the memory cell array. The new column voltage control method enables not only leakage current but also the operating current to be reduced by performing column direction voltage control.

A 64KB (32KB W 2) dual-port SRAM test chip has been created using a 90nm CMOS process.





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