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Arteris spins packet-based on-chip net IP

Posted: 04 Mar 2004 ?? ?Print Version ?Bookmark and Share

Keywords:arteris sa? on-chip network?

Arteris SA, an IP vendor in Paris, is commercializing a packet-based on-chip network as an alternative to the hierarchies of buses.

By using asynchronous links between switching blocks, the company has in effect implemented one of the SoC research community's favorite algorithms: a globally asynchronous, locally synchronous (Gals) interconnect. In this architecture, functional blocks are designed in the conventional manner using synchronous design and standard tools. But instead of connecting to microprocessor-style synchronous buses, the blocks in a Gals architecture have, in effect, network interfaces that connect them to an on-chip packet network.

The concept of replacing buses or point-to-point wiring on system-level ICs with an on-chip network has been bubbling away in the academic community for years. It has been recognized that too many design and physical resources are going into interblock wiring in SoCs, and that the results are increasingly unpredictable.

Distributed control

The packet-based network that Arteris has developed is composed of links, controllers and bridges, all woven into a scalable homogeneous packet-switch fabric, said vice president of marketing and sales Kent Jaeger. Unlike hierarchical bus architectures, there is no fixed topology: the network is created for each individual SoC design. And there is no central controller. Instead, control is distributed across the switch blocks. Also unlike buses, there can be a huge number of concurrent paths, giving higher aggregate bandwidth than even bus architectures with lots of segments and bridges.

Arteris does not exclude industry-standard buses, however, but incorporates them via bridge blocks - as if the buses were themselves blocks of user IP. Thus, a design team doesn't have to tear up an Amba-based subsystem and redesign it, but can simply add a bridge to connect it into the network-on-chip.

Thus the packet network can offer significantly higher bandwidth and greater determinism than a bus architecture, Arteris said. Because it is deployed as IP in a scalable form, there should also be a significant reduction in design time - particularly in signal integrity and timing closure. Some closure issues just cease to exist when there aren't huge synchronous devices - that is, buses - spanning vast areas of the die. The network also brings about a 10 to 20 percent increase in silicon overhead compared with the simplest alternatives, according to CEO Alain Fanet.

There were considerable challenges in designing such a network architecture, Fanet said. "After all," he pointed out, "you can't just drop a packet and restart when you are carrying both data and control flows inside a chip. You have to always know the state of the chip, and you have to be able to guarantee quality-of-service."

- Ron Wilson

EE Times

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