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Silvaco offers open-source Verilog-A models

Posted: 05 Mar 2004 ?? ?Print Version ?Bookmark and Share

Keywords:verilog-a? silvaco international? accellera? verilog-ams 2.1? bsim3?

Moving to help speed adoption of the Verilog-A analog modeling language, Silvaco International is offering nine Verilog-A device models for free download under open-source distribution. The models are compliant with Accellera's Verilog-AMS 2.1 specification.

The models include complete source code for BSIM3, BSIM4, EKV, RPI-TFT, Level 3 MOS, Gummel-Poon, Mextram, and diode. Users are invited to download these active device models, study them, use them, modify them, and submit improvements to Silvaco for posting. Users may not, however, resell or license the models for commercial purposes.

Verilog-A simplifies the development of compact models, which are used by Spice simulators to model the behavior of devices such as transistors, diodes, capacitors, inductors, and resistors. Such models are typically written in the C language, and compiled directly into Spice. Models must generally be recompiled, re-linked, and re-verified if there are any changes to model source code.

With Verilog-A, in contrast, model developers without access to a Spice simulator can study and verify compact models in an interactive debugging environment. The Verilog-A model can then be dynamically linked into a Spice simulator as a new model. Multiple Spice simulators can use the same model.

The open-source models can be downloaded from Silvaco's support website. The models have been developed and tested using Silvaco's SmartSpice simulator.

- Richard Goering

EE Times

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