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Control plane bridge chips span to SPI 4.2Chipsets extend fiber with copper in last mile

Posted: 11 Mar 2004 ?? ?Print Version ?Bookmark and Share

Keywords:cavium networks? spi 4.2? pci-x? pci? spi3?

Security processor vendor Cavium has tapped into its I/O connectivity and packet-processing experience to craft a device family that provides transparent bridging between an SPI 4.2 device and existing PCI-X, PCI and SPI 3 interfaces-or that bridges an OEM's proprietary SPI 4.2 interface to a standard SPI 4.2 link-on network processors and other dataplane-processing products.

The SPI 4.2 interface, developed by the Optical Internetworking Forum, is becoming the de facto option for linking packet processors, switch fabrics and lookaside devices in networking applications. But there are still a number of components, such as framers, that rely on older interfaces like SPI 3 to connect to an NPU. Additionally, many network processors rely on a PCI interface to link up to an X86-based control-plane processor, said Rajneesh Gaur, product-line-marketing manager at Cavium Networks.

In either case, designers have used an FPGA to implement the glue logic between the control-plane processor or framer and the NPU, but the power and expense of an FPGA can be unattractive to some OEMs, Gaur said.

With its development of the Golden Gate SPI bridge processor family, Cavium is giving designers an alternative. The family includes transparent devices that simply bridge interfaces and intelligent devices that allow designers to manipulate packets to achieve a customized interface. Intelligence functionality can be added as a firmware upgrade to the transparent bridging chips, Gaur said.

The SPI bridging devices tap the same I/O technology that Cavium used to develop its Nitrox family of security processors. The intelligent Golden Gate devices also include a stripped-down version of the Nitrox family's core. All SPI bridging parts include 1MB of on-chip buffer memory, which allows the bridge chips to handle line-rate traffic, Gaur added.

The family includes four devices that provide transparent bridging between existing PCI-X, PCI, and SPI 3 interfaces and an SPI 4.2 device. The family also includes a device that can provide bridging between a proprietary SPI 4.2 interface developed by an OEM and a standard SPI 4.2 interface.

While some companies will clamor for an SPI bridging device, others will still rely on FPGAs for glue logic, said Sanjay Iyer, senior analyst for The Linley Group.

"This is clearly an opportunistic move for Cavium," Iyer said.

While Cavium may not be targeting a big market, Iyer said the company may do well with its bridging devices. The low development cost associated with the products - Cavium said they were made in six months - makes it a less risky move, Iyer said.

Astute Networks Inc., a developer of silicon-based acceleration technology, is using the bridging chips to link a Gigabit Ethernet MAC device from Intel Corp. to an internally developed protocol-processing engines.

Cavium's Golden Gate SPI bridging devices are manufactured in a 0.13?m process and are delivered in pin-compatible, 1,096-ball heat-slug BGA packages. The chips are sampling now, and volume production is expected to start in April.

The transparent chips are priced from $100 to $150 apiece in volumes, and the intelligent chips will carry a 15 percent premium.

- Robert Keenan

EE Times

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